gtsoul-tech
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3d60d4f3be
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arm supervector explicit constructor
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2024-05-14 09:53:08 +03:00 |
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gtsoul-tech
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ee8bc59ee0
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x86 explicit constructor supervector
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2024-05-14 09:28:13 +03:00 |
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Yoan Picchi
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8e5abfebf0
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Add truffle SVE implementation
Signed-off-by: Yoan Picchi <yoan.picchi@arm.com>
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2024-01-09 16:50:03 +00:00 |
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Konstantinos Margaritis
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f57928ea08
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fix SIMDe emulation builds on Arm, add native translation from x86 for comparison
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2023-11-27 12:21:58 +00:00 |
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Konstantnos Margaritis
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b068087240
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add SIMDe ports of simd_utils and supervector
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2023-11-21 17:12:04 +00:00 |
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Konstantinos Margaritis
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e6cfd11948
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prefix assume_aligned to avoid clash with std::assume_aligned in c++20
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2022-11-01 10:29:22 +00:00 |
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Konstantinos Margaritis
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dc6b8ae92d
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optimize comparemask implementation, clean up code, use union types instead of casts
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2022-09-07 02:02:11 +03:00 |
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Danila Kutenin
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8a49e20bcd
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Fix formatting of a couple files
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2022-06-26 22:59:58 +00:00 |
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Danila Kutenin
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49eb18ee4f
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Optimize vectorscan for aarch64 by using shrn instruction
This optimization is based on the thread
https://twitter.com/Danlark1/status/1539344279268691970 and uses
shift right and narrow by 4 instruction https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/SHRN--SHRN2--Shift-Right-Narrow--immediate--
To achieve that, I needed to redesign a little movemask into comparemask
and have an additional step towards mask iteration. Our benchmarks
showed 10-15% improvement on average for long matches.
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2022-06-26 22:55:45 +00:00 |
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Konstantinos Margaritis
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4aa32275f1
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use same definition of the union for all types
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2021-12-02 18:00:02 +02:00 |
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Konstantinos Margaritis
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0221dc1771
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fix misompilations with clang++, as it is more strict
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2021-12-01 23:22:15 +02:00 |
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Apostolos Tapsas
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0287724413
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WIP:tracking last bugs in failing tests for release build
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2021-11-16 15:24:22 +00:00 |
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apostolos
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e09d8674b4
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resolving conficts after merging
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2021-11-13 18:58:22 +02:00 |
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Konstantinos Margaritis
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7b65b298c1
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add arm vector types in union, avoid -flax-conversions, fix castings
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2021-11-01 16:52:17 +02:00 |
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Vectorcamp
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2231f7c024
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compile fixes for vsc port
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2021-10-14 13:53:55 +03:00 |
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Konstantinos Margaritis
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577e03e0c7
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rearrange method declarations
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2021-10-12 11:51:35 +03:00 |
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Konstantinos Margaritis
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67e0674df8
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Changes/Additions to SuperVector class * added ==,!=,>=,>,<=,< operators * reworked shift operators to be more uniform and orthogonal, like Arm ISA * Added Unroller class to allow handling of multiple cases but avoid code duplication * pshufb method can now emulate Intel or not (avoids one instruction).
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2021-10-12 11:51:34 +03:00 |
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Konstantinos Margaritis
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e7161fdfec
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initial SSE/AVX2 implementation
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2021-10-12 11:51:34 +03:00 |
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Konstantinos Margaritis
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603bc14cdd
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fix failing corner case, add pshufb_maskz()
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2021-10-12 11:51:34 +03:00 |
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Konstantinos Margaritis
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f8ce0bb922
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minor fixes, add 2 constructors from half size vectors
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2021-10-12 11:51:34 +03:00 |
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Konstantinos Margaritis
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ebb1b84ae3
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provide an {l,r}shift128_var() to fix immediate value build failure in loadu_maskz
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2021-10-12 11:51:34 +03:00 |
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Konstantinos Margaritis
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6c51f7f591
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add {l,r}shift128()+tests, rename printv_u64() to print64()
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2021-10-12 11:51:34 +03:00 |
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Konstantinos Margaritis
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c45e72775f
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convert print helper functions to class methods
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2021-10-12 11:51:34 +03:00 |
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Konstantinos Margaritis
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28b2949396
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harmonise syntax of x86 SuperVector impl.cpp like arm, fix alignr, define printv_* functions when on debug mode only
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2021-10-12 11:51:34 +03:00 |
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Konstantinos Margaritis
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2753dbb3b0
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rename supervector class header, use dup_*() functions names instead of set1_*(), minor fixes
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2021-10-12 11:51:34 +03:00 |
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