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https://github.com/VectorCamp/vectorscan.git
synced 2025-09-29 19:24:25 +03:00
Shuffle simd and SuperVector implementetions as well as their test realy fixed
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committed by
apostolos
parent
d43d6733b6
commit
1eb3b19f63
@@ -187,7 +187,7 @@ TEST(Shuffle, PackedExtract128_1) {
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// shuffle a single 1 bit to the front
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m128 permute, compare;
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build_pshufb_masks_onebit(i, &permute, &compare);
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EXPECT_EQ(1U, packedExtract128(setbit<m128>(i), permute, compare));
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EXPECT_EQ(1U, packedExtract128(setbit<m128>(i), permute, compare));
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EXPECT_EQ(1U, packedExtract128(ones128(), permute, compare));
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// we should get zero out of these cases
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EXPECT_EQ(0U, packedExtract128(zeroes128(), permute, compare));
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@@ -199,7 +199,7 @@ TEST(Shuffle, PackedExtract128_1) {
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}
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}
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/*
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TEST(Shuffle, PackedExtract_templatized_128_1) {
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// Try all possible one-bit masks
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for (unsigned int i = 0; i < 128; i++) {
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@@ -218,7 +218,7 @@ TEST(Shuffle, PackedExtract_templatized_128_1) {
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}
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}
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}
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*/
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#if defined(HAVE_AVX2)
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@@ -849,15 +849,22 @@ TEST(SimdUtilsTest, pshufb_m128) {
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}
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u8 vec2[16];
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for (int i=0; i<16; i++) {
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vec2[i]=i + (rand() % 16 + 0);
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}
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vec2[i]=i + (rand() % 15 + 0);
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}
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m128 v1 = loadu128(vec);
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m128 v2 = loadu128(vec2);
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m128 vres = pshufb_m128(v1, v2);
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m128 vres = pshufb_m128(v1, v2);
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u8 res[16];
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store128(res, vres);
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storeu128(res, vres);
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for (int i=0; i<16; i++) {
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ASSERT_EQ(vec[vec2[i] % 16 ], res[i]);
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if(vec2[i] & 0x80){
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ASSERT_EQ(res[i], 0);
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}else{
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ASSERT_EQ(vec[vec2[i] % 16 ], res[i]);
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}
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}
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}
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@@ -286,7 +286,11 @@ TEST(SuperVectorUtilsTest,pshufb128c) {
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auto SP2 = SuperVector<16>::loadu(vec2);
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auto SResult = SP1.template pshufb<true>(SP2);
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for (int i=0; i<16; i++) {
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ASSERT_EQ(vec[vec2[i] % 16 ],SResult.u.u8[i]);
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if(vec2[i] & 0x80){
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ASSERT_EQ(SResult.u.u8[i], 0);
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}else{
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ASSERT_EQ(vec[vec2[i] % 16 ],SResult.u.u8[i]);
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}
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}
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}
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