* Add regression test for double shufti
It tests for false positive at vector edges.
Signed-off-by: Yoan Picchi <yoan.picchi@arm.com>
* Fix double shufti reporting false positives
Double shufti used to offset one vector, resulting in losing one character
at the end of every vector. This was replaced by a magic value indicating a
match. This meant that if the first char of a pattern fell on the last char of
a vector, double shufti would assume the second character is present and
report a match.
This patch fixes it by keeping the previous vector and feeding its data to the
new one when we shift it, preventing any loss of data.
Signed-off-by: Yoan Picchi <yoan.picchi@arm.com>
* vshl() will call the correct implementation
* implement missing vshr_512_imm(), simplifies caller x86 code
* Fix x86 case, use alignr instead
* it's the reverse, the avx512 alignr is incorrect, need to fix
* Make shufti's OR reduce size agnostic
Signed-off-by: Yoan Picchi <yoan.picchi@arm.com>
* Fix test's array size
Signed-off-by: Yoan Picchi <yoan.picchi@arm.com>
* Fix AVX2/AVX512 alignr implementations and unit tests
* Fix Power VSX alignr
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Signed-off-by: Yoan Picchi <yoan.picchi@arm.com>
Co-authored-by: Konstantinos Margaritis <konstantinos@vectorcamp.gr>
Multiple AVX512VBMI-related fixes:
src/nfa/mcsheng_compile.cpp: No need for an assert here, impl_id can be set to 0
src/nfa/nfa_api_queue.h: Make sure this compiles on both C++ and C
src/nfagraph/ng_fuzzy.cpp: Fix compilation error when DEBUG_OUTPUT=on
src/runtime.c: Fix crash when data == NULL
unit/internal/sheng.cpp: Unit test has to enable AVX512VBMI manually as autodetection does not get trigger, this causes test to fail
src/fdr/teddy_fat.cpp: AVX512 loads need to be 64-bit aligned, caused a crash on clang-18
Fixed out of bounds read in AVX512VBMI version of fdr_exec_fat_teddy (#322)
* Replaced the 32 byte read with a properly truncated mapped read
* Added a unit test
Co-authored-by: Rafał Dowgird <rafal.dowgird@rtbhouse.com>
Revert the code that produced the regression error in #317
Add the regression error to a unit test regressions.cpp along with the rebar tests
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Co-authored-by: gtsoul-tech <gtsoulkanakis@gmail.com>
* Revert "Fix noodle SVE2 off by one bug"
This patch was fixing the bug when it happens at the end of the buffer
but it wasn't fixing it when we do scanDoubleOnce before the main loop
The next patch fix this bug for both case instead
This reverts commit 48dd0e5ff0bc1995d62461c92cfb76d44d1d0105.
* Fix noodle spurious match with \0 chars for SVE2
When sve2's noodle process a non full vector (before the main loop or
at the end of it), a fake \0 was being parsed, trigerring a match for
pattern that ended with \0. This patch fix this.
Signed-off-by: Yoan Picchi <yoan.picchi@arm.com>
---------
Signed-off-by: Yoan Picchi <yoan.picchi@arm.com>
Vectorscan requires SSE4.2 as a minimum on x86_64. For Hyperscan this
used to be SSSE3.
Applications that use the library call hs_valid_platform() to check if
the CPU fulfils this minimum requirement. However, when Vectorscan
upgraded to SSE4.2, the check was not updated. This leads to the library
trying to execute instructions that are not supported, resulting in the
application to crash.
This might not have been noticed as the CPUs that do not support SSE4.2
are rather old and unlikely to run any load where performance is an
issue. However, I believe that the library should not let the
application crash.
Signed-off-by: Michael Tremer <michael.tremer@ipfire.org>
Vectorscan used to reject such pattern because they were being compared
to "" and found to be an empty string. We now check the pattern length
instead.
Signed-off-by: Yoan Picchi <yoan.picchi@arm.com>
By using svmatch on 16 bit lanes with a 8 bit predicate, we end up
including an undefined character in the pattern checks. The inactive
lane after load contains an undefined value, usually \0. Patterns
using \0 as the last character would then match this spurious
character, returning a match beyond the buffer's end. The fix checks
for such matches and rejects them.
Signed-off-by: Yoan Picchi <yoan.picchi@arm.com>
This allows the use of SIMDE library to emulate SSSE3/SSE4.2 instructions on SSE2-only (x86-64-v2) hardware.
---------
Co-authored-by: G.E <gregory.economou@vectorcamp.gr>
Co-authored-by: Konstantinos Margaritis <konstantinos@vectorcamp.gr>
256b wide SVE vectors allow some simplification of truffle.
Up to 40% speedup on graviton3. Going from 12500 MB/s to 17000 MB/s
onhe microbenchmark.
SVE2 also offer this capability for 128b vector with a speedup around
25% compared to normal SVE
Add unit tests and benchmark for this wide variant
Signed-off-by: Yoan Picchi <yoan.picchi@arm.com>
subtely clever (or else totally useless all these years), when we
see which of the two we might delete that assert entirely. for now
put it back as it was.
