mirror of
https://github.com/VectorCamp/vectorscan.git
synced 2025-09-30 03:34:25 +03:00
move cpuid stuff to util/arch/x86
This commit is contained in:
Konstantinos Margaritis
159
src/util/arch/x86/cpuid_flags.c
Normal file
159
src/util/arch/x86/cpuid_flags.c
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@@ -0,0 +1,159 @@
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/*
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* Copyright (c) 2015-2017, Intel Corporation
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* * Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Intel Corporation nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "cpuid_flags.h"
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#include "cpuid_inline.h"
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#include "ue2common.h"
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#include "hs_compile.h" // for HS_MODE_ flags
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#include "hs_internal.h"
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#include "util/arch.h"
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#if !defined(_WIN32) && !defined(CPUID_H_)
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#include <cpuid.h>
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#endif
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u64a cpuid_flags(void) {
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u64a cap = 0;
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if (check_avx2()) {
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DEBUG_PRINTF("AVX2 enabled\n");
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cap |= HS_CPU_FEATURES_AVX2;
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}
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if (check_avx512()) {
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DEBUG_PRINTF("AVX512 enabled\n");
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cap |= HS_CPU_FEATURES_AVX512;
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}
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#if !defined(FAT_RUNTIME) && !defined(HAVE_AVX2)
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cap &= ~HS_CPU_FEATURES_AVX2;
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#endif
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#if (!defined(FAT_RUNTIME) && !defined(HAVE_AVX512)) || \
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(defined(FAT_RUNTIME) && !defined(BUILD_AVX512))
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cap &= ~HS_CPU_FEATURES_AVX512;
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#endif
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return cap;
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}
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struct family_id {
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u32 full_family;
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u32 full_model;
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u32 tune;
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};
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/* from table 35-1 of the Intel 64 and IA32 Arch. Software Developer's Manual
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* and "Intel Architecture and Processor Identification With CPUID Model and
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* Family Numbers" */
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static const struct family_id known_microarch[] = {
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{ 0x6, 0x37, HS_TUNE_FAMILY_SLM }, /* baytrail */
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{ 0x6, 0x4A, HS_TUNE_FAMILY_SLM }, /* silvermont */
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{ 0x6, 0x4C, HS_TUNE_FAMILY_SLM }, /* silvermont */
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{ 0x6, 0x4D, HS_TUNE_FAMILY_SLM }, /* avoton, rangley */
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{ 0x6, 0x5A, HS_TUNE_FAMILY_SLM }, /* silvermont */
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{ 0x6, 0x5D, HS_TUNE_FAMILY_SLM }, /* silvermont */
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{ 0x6, 0x5C, HS_TUNE_FAMILY_GLM }, /* goldmont */
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{ 0x6, 0x5F, HS_TUNE_FAMILY_GLM }, /* denverton */
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{ 0x6, 0x3C, HS_TUNE_FAMILY_HSW }, /* haswell */
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{ 0x6, 0x45, HS_TUNE_FAMILY_HSW }, /* haswell */
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{ 0x6, 0x46, HS_TUNE_FAMILY_HSW }, /* haswell */
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{ 0x6, 0x3F, HS_TUNE_FAMILY_HSW }, /* haswell Xeon */
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{ 0x6, 0x3E, HS_TUNE_FAMILY_IVB }, /* ivybridge Xeon */
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{ 0x6, 0x3A, HS_TUNE_FAMILY_IVB }, /* ivybridge */
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{ 0x6, 0x2A, HS_TUNE_FAMILY_SNB }, /* sandybridge */
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{ 0x6, 0x2D, HS_TUNE_FAMILY_SNB }, /* sandybridge Xeon */
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{ 0x6, 0x3D, HS_TUNE_FAMILY_BDW }, /* broadwell Core-M */
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{ 0x6, 0x47, HS_TUNE_FAMILY_BDW }, /* broadwell */
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{ 0x6, 0x4F, HS_TUNE_FAMILY_BDW }, /* broadwell xeon */
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{ 0x6, 0x56, HS_TUNE_FAMILY_BDW }, /* broadwell xeon-d */
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{ 0x6, 0x4E, HS_TUNE_FAMILY_SKL }, /* Skylake Mobile */
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{ 0x6, 0x5E, HS_TUNE_FAMILY_SKL }, /* Skylake Core/E3 Xeon */
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{ 0x6, 0x55, HS_TUNE_FAMILY_SKX }, /* Skylake Xeon */
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{ 0x6, 0x8E, HS_TUNE_FAMILY_SKL }, /* Kabylake Mobile */
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{ 0x6, 0x9E, HS_TUNE_FAMILY_SKL }, /* Kabylake desktop */
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};
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#ifdef DUMP_SUPPORT
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static UNUSED
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const char *dumpTune(u32 tune) {
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#define T_CASE(x) case x: return #x;
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switch (tune) {
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T_CASE(HS_TUNE_FAMILY_SLM);
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T_CASE(HS_TUNE_FAMILY_GLM);
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T_CASE(HS_TUNE_FAMILY_HSW);
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T_CASE(HS_TUNE_FAMILY_SNB);
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T_CASE(HS_TUNE_FAMILY_IVB);
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T_CASE(HS_TUNE_FAMILY_BDW);
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T_CASE(HS_TUNE_FAMILY_SKL);
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T_CASE(HS_TUNE_FAMILY_SKX);
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}
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#undef T_CASE
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return "unknown";
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}
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#endif
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u32 cpuid_tune(void) {
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unsigned int eax, ebx, ecx, edx;
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cpuid(1, 0, &eax, &ebx, &ecx, &edx);
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u32 family = (eax >> 8) & 0xf;
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u32 model = 0;
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if (family == 0x6 || family == 0xf) {
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model = ((eax >> 4) & 0xf) | ((eax >> 12) & 0xf0);
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} else {
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model = (eax >> 4) & 0xf;
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}
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DEBUG_PRINTF("family = %xh model = %xh\n", family, model);
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for (u32 i = 0; i < ARRAY_LENGTH(known_microarch); i++) {
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if (family != known_microarch[i].full_family) {
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continue;
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}
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if (model != known_microarch[i].full_model) {
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continue;
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}
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u32 tune = known_microarch[i].tune;
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DEBUG_PRINTF("found tune flag %s\n", dumpTune(tune) );
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return tune;
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}
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return HS_TUNE_FAMILY_GENERIC;
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}
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55
src/util/arch/x86/cpuid_flags.h
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55
src/util/arch/x86/cpuid_flags.h
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@@ -0,0 +1,55 @@
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/*
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* Copyright (c) 2015-2017, Intel Corporation
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* * Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Intel Corporation nor the names of its contributors
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* may be used to endorse or promote products derived from this software
|
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef UTIL_CPUID_H_
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#define UTIL_CPUID_H_
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#include "ue2common.h"
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#if !defined(_WIN32) && !defined(CPUID_H_)
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#include <cpuid.h>
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/* system header doesn't have a header guard */
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#define CPUID_H_
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#endif
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/* returns HS_CPU_FEATURES_* mask. */
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u64a cpuid_flags(void);
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u32 cpuid_tune(void);
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#ifdef __cplusplus
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} /* extern "C" */
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#endif
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#endif /* UTIL_CPUID_H_ */
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214
src/util/arch/x86/cpuid_inline.h
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214
src/util/arch/x86/cpuid_inline.h
Normal file
@@ -0,0 +1,214 @@
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/*
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* Copyright (c) 2017, Intel Corporation
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* * Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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||||
* notice, this list of conditions and the following disclaimer in the
|
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Intel Corporation nor the names of its contributors
|
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* may be used to endorse or promote products derived from this software
|
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef CPUID_INLINE_H_
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#define CPUID_INLINE_H_
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#include "ue2common.h"
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#include "cpuid_flags.h"
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#if !defined(_WIN32) && !defined(CPUID_H_)
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#include <cpuid.h>
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/* system header doesn't have a header guard */
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#define CPUID_H_
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#endif
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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static inline
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void cpuid(unsigned int op, unsigned int leaf, unsigned int *eax,
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unsigned int *ebx, unsigned int *ecx, unsigned int *edx) {
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#ifndef _WIN32
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__cpuid_count(op, leaf, *eax, *ebx, *ecx, *edx);
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#else
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int a[4];
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__cpuidex(a, op, leaf);
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*eax = a[0];
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*ebx = a[1];
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*ecx = a[2];
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*edx = a[3];
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#endif
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}
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// ECX
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#define CPUID_SSE3 (1 << 0)
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#define CPUID_SSSE3 (1 << 9)
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#define CPUID_SSE4_1 (1 << 19)
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#define CPUID_SSE4_2 (1 << 20)
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#define CPUID_POPCNT (1 << 23)
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#define CPUID_XSAVE (1 << 27)
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#define CPUID_AVX (1 << 28)
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// EDX
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#define CPUID_FXSAVE (1 << 24)
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#define CPUID_SSE (1 << 25)
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#define CPUID_SSE2 (1 << 26)
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#define CPUID_HTT (1 << 28)
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// Structured Extended Feature Flags Enumeration Leaf ECX values
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#define CPUID_BMI (1 << 3)
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#define CPUID_AVX2 (1 << 5)
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#define CPUID_BMI2 (1 << 8)
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// Structured Extended Feature Flags Enumeration Leaf EBX values
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#define CPUID_AVX512F (1 << 16)
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#define CPUID_AVX512BW (1 << 30)
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// Extended Control Register 0 (XCR0) values
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#define CPUID_XCR0_SSE (1 << 1)
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#define CPUID_XCR0_AVX (1 << 2)
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#define CPUID_XCR0_OPMASK (1 << 5) // k-regs
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#define CPUID_XCR0_ZMM_Hi256 (1 << 6) // upper 256 bits of ZMM0-ZMM15
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#define CPUID_XCR0_Hi16_ZMM (1 << 7) // ZMM16-ZMM31
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#define CPUID_XCR0_AVX512 \
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(CPUID_XCR0_OPMASK | CPUID_XCR0_ZMM_Hi256 | CPUID_XCR0_Hi16_ZMM)
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static inline
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u64a xgetbv(u32 op) {
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#if defined(_WIN32) || defined(__INTEL_COMPILER)
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return _xgetbv(op);
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#else
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u32 a, d;
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__asm__ volatile (
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"xgetbv\n"
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: "=a"(a),
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"=d"(d)
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: "c"(op));
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return ((u64a)d << 32) + a;
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#endif
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}
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static inline
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int check_avx2(void) {
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#if defined(__INTEL_COMPILER)
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return _may_i_use_cpu_feature(_FEATURE_AVX2);
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#else
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unsigned int eax, ebx, ecx, edx;
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cpuid(1, 0, &eax, &ebx, &ecx, &edx);
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/* check AVX is supported and XGETBV is enabled by OS */
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if ((ecx & (CPUID_AVX | CPUID_XSAVE)) != (CPUID_AVX | CPUID_XSAVE)) {
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DEBUG_PRINTF("AVX and XSAVE not supported\n");
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return 0;
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}
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/* check that SSE and AVX registers are enabled by OS */
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u64a xcr0 = xgetbv(0);
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if ((xcr0 & (CPUID_XCR0_SSE | CPUID_XCR0_AVX)) !=
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(CPUID_XCR0_SSE | CPUID_XCR0_AVX)) {
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DEBUG_PRINTF("SSE and AVX registers not enabled\n");
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return 0;
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}
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/* ECX and EDX contain capability flags */
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ecx = 0;
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cpuid(7, 0, &eax, &ebx, &ecx, &edx);
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if (ebx & CPUID_AVX2) {
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DEBUG_PRINTF("AVX2 enabled\n");
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return 1;
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}
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return 0;
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#endif
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}
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static inline
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int check_avx512(void) {
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/*
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* For our purposes, having avx512 really means "can we use AVX512BW?"
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*/
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#if defined(__INTEL_COMPILER)
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return _may_i_use_cpu_feature(_FEATURE_AVX512BW | _FEATURE_AVX512VL);
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#else
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unsigned int eax, ebx, ecx, edx;
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cpuid(1, 0, &eax, &ebx, &ecx, &edx);
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/* check XSAVE is enabled by OS */
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if (!(ecx & CPUID_XSAVE)) {
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DEBUG_PRINTF("AVX and XSAVE not supported\n");
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return 0;
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}
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/* check that AVX 512 registers are enabled by OS */
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u64a xcr0 = xgetbv(0);
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if ((xcr0 & CPUID_XCR0_AVX512) != CPUID_XCR0_AVX512) {
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DEBUG_PRINTF("AVX512 registers not enabled\n");
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return 0;
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}
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/* ECX and EDX contain capability flags */
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ecx = 0;
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cpuid(7, 0, &eax, &ebx, &ecx, &edx);
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if (!(ebx & CPUID_AVX512F)) {
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DEBUG_PRINTF("AVX512F (AVX512 Foundation) instructions not enabled\n");
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return 0;
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}
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if (ebx & CPUID_AVX512BW) {
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DEBUG_PRINTF("AVX512BW instructions enabled\n");
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return 1;
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}
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return 0;
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#endif
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}
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static inline
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int check_ssse3(void) {
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unsigned int eax, ebx, ecx, edx;
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cpuid(1, 0, &eax, &ebx, &ecx, &edx);
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return !!(ecx & CPUID_SSSE3);
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}
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static inline
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int check_sse42(void) {
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unsigned int eax, ebx, ecx, edx;
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cpuid(1, 0, &eax, &ebx, &ecx, &edx);
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return !!(ecx & CPUID_SSE4_2);
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}
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static inline
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int check_popcnt(void) {
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unsigned int eax, ebx, ecx, edx;
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cpuid(1, 0, &eax, &ebx, &ecx, &edx);
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return !!(ecx & CPUID_POPCNT);
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}
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#ifdef __cplusplus
|
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} /* extern "C" */
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#endif
|
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||||
#endif /* CPUID_INLINE_H_ */
|
||||
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