mirror of
https://github.com/VectorCamp/vectorscan.git
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move x86 arch and SIMD types to x86 arch folder
This commit is contained in:
Konstantinos Margaritis
parent
c00683d739
commit
2d89df44ae
@ -33,58 +33,9 @@
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#ifndef UTIL_ARCH_H_
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#define UTIL_ARCH_H_
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#if defined(__SSE2__) || defined(_M_X64) || (_M_IX86_FP >= 2)
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#define HAVE_SSE2
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#if defined(__i386__) || defined(__x86_64__)
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#include "util/arch/x86/x86.h"
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#endif
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#if defined(__SSE4_1__) || (defined(_WIN32) && defined(__AVX__))
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#define HAVE_SSE41
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#endif
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#endif // UTIL_ARCH_X86_H_
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#if defined(__SSE4_2__) || (defined(_WIN32) && defined(__AVX__))
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#define HAVE_SSE42
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#endif
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#if defined(__AVX__)
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#define HAVE_AVX
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#endif
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#if defined(__AVX2__)
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#define HAVE_AVX2
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#endif
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#if defined(__AVX512BW__)
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#define HAVE_AVX512
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#endif
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#if defined(__AVX512VBMI__)
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#define HAVE_AVX512VBMI
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#endif
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/*
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* ICC and MSVC don't break out POPCNT or BMI/2 as separate pre-def macros
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*/
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#if defined(__POPCNT__) || \
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(defined(__INTEL_COMPILER) && defined(__SSE4_2__)) || \
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(defined(_WIN32) && defined(__AVX__))
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#define HAVE_POPCOUNT_INSTR
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#endif
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#if defined(__BMI__) || (defined(_WIN32) && defined(__AVX2__)) || \
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(defined(__INTEL_COMPILER) && defined(__AVX2__))
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#define HAVE_BMI
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#endif
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#if defined(__BMI2__) || (defined(_WIN32) && defined(__AVX2__)) || \
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(defined(__INTEL_COMPILER) && defined(__AVX2__))
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#define HAVE_BMI2
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#endif
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/*
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* MSVC uses a different form of inline asm
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*/
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#if defined(_WIN32) && defined(_MSC_VER)
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#define NO_ASM
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#endif
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#endif // UTIL_ARCH_H_
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45
src/util/arch/x86/simd_types.h
Normal file
45
src/util/arch/x86/simd_types.h
Normal file
@ -0,0 +1,45 @@
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/*
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* Copyright (c) 2015-2017, Intel Corporation
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* * Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Intel Corporation nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef SIMD_TYPES_X86_H
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#define SIMD_TYPES_X86_H
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#if !defined(m128) && defined(HAVE_SSE2)
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typedef __m128i m128;
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#endif
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#if !defined(m128) && defined(HAVE_AVX2)
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typedef __m256i m256;
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#endif
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#if !defined(m512) && defined(HAVE_AVX512)
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typedef __m512i m512;
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#endif
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#endif /* SIMD_TYPES_H */
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96
src/util/arch/x86/x86.h
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96
src/util/arch/x86/x86.h
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@ -0,0 +1,96 @@
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/*
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* Copyright (c) 2017-2020, Intel Corporation
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* * Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Intel Corporation nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/** \file
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* \brief Per-platform architecture definitions
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*/
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#ifndef UTIL_ARCH_X86_H_
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#define UTIL_ARCH_X86_H_
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#if defined(__SSE2__) || defined(_M_X64) || (_M_IX86_FP >= 2)
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#define HAVE_SSE2
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#define HAVE_SIMD_128_BITS
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#endif
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#if defined(__SSE4_1__) || (defined(_WIN32) && defined(__AVX__))
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#define HAVE_SSE41
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#define HAVE_SIMD_128_BITS
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#endif
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#if defined(__SSE4_2__) || (defined(_WIN32) && defined(__AVX__))
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#define HAVE_SSE42
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#define HAVE_SIMD_128_BITS
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#endif
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#if defined(__AVX__)
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#define HAVE_AVX
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#define HAVE_SIMD_256_BITS
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#endif
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#if defined(__AVX2__)
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#define HAVE_AVX2
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#define HAVE_SIMD_256_BITS
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#endif
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#if defined(__AVX512BW__)
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#define HAVE_AVX512
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#define HAVE_SIMD_512_BITS
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#endif
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#if defined(__AVX512VBMI__)
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#define HAVE_AVX512VBMI
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#endif
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/*
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* ICC and MSVC don't break out POPCNT or BMI/2 as separate pre-def macros
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*/
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#if defined(__POPCNT__) || \
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(defined(__INTEL_COMPILER) && defined(__SSE4_2__)) || \
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(defined(_WIN32) && defined(__AVX__))
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#define HAVE_POPCOUNT_INSTR
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#endif
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#if defined(__BMI__) || (defined(_WIN32) && defined(__AVX2__)) || \
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(defined(__INTEL_COMPILER) && defined(__AVX2__))
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#define HAVE_BMI
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#endif
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#if defined(__BMI2__) || (defined(_WIN32) && defined(__AVX2__)) || \
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(defined(__INTEL_COMPILER) && defined(__AVX2__))
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#define HAVE_BMI2
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#endif
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/*
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* MSVC uses a different form of inline asm
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*/
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#if defined(_WIN32) && defined(_MSC_VER)
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#define NO_ASM
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#endif
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#endif // UTIL_ARCH_X86_H_
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@ -34,22 +34,20 @@
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#include "util/intrinsics.h"
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#include "ue2common.h"
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#if defined(HAVE_SSE2)
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typedef __m128i m128;
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#else
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#if defined(__i386__) || defined(__x86_64__)
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#include "util/arch/x86/simd_types.h"
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#endif
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#if !defined(m128) && !defined(HAVE_SIMD_128_BITS)
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typedef struct ALIGN_DIRECTIVE {u64a hi; u64a lo;} m128;
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#endif
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#if defined(HAVE_AVX2)
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typedef __m256i m256;
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#else
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#if !defined(m256) && !defined(HAVE_SIMD_256_BITS)
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typedef struct ALIGN_AVX_DIRECTIVE {m128 lo; m128 hi;} m256;
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#endif
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typedef struct {m128 lo; m128 mid; m128 hi;} m384;
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#if defined(HAVE_AVX512)
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typedef __m512i m512;
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#else
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#if !defined(m512) && !defined(HAVE_SIMD_512_BITS)
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typedef struct ALIGN_ATTR(64) {m256 lo; m256 hi;} m512;
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#endif
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@ -38,10 +38,10 @@
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#endif
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#include "config.h"
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#include "util/arch.h"
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#include "ue2common.h"
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#include "simd_types.h"
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#include "unaligned.h"
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#include "util/arch.h"
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#include "util/intrinsics.h"
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#include <string.h> // for memcpy
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