mirror of
https://github.com/VectorCamp/vectorscan.git
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Co-authored-by: yangwenqing <yangwenqing@loongson.cn> Signed-off-by: Leslie Zhai <zhaixiang@loongson.cn> Signed-off-by: yangwenqing <yangwenqing@loongson.cn>
215 lines
5.5 KiB
C
215 lines
5.5 KiB
C
/*
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* Copyright (c) 2015-2017, Intel Corporation
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* Copyright (c) 2020-2021, VectorCamp PC
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* Copyright (c) 2023, Loongson Technology
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* * Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Intel Corporation nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/** \file
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* \brief Bit-twiddling primitives (ctz, compress etc)
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*/
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#ifndef BITUTILS_ARCH_LOONGARCH64_H
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#define BITUTILS_ARCH_LOONGARCH64_H
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#include "ue2common.h"
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#include "util/popcount.h"
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#include "util/arch.h"
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#include "util/intrinsics.h"
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#include "util/arch/common/bitutils.h"
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static really_inline
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u32 clz32_impl(u32 x) {
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return clz32_impl_c(x);
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}
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static really_inline
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u32 clz64_impl(u64a x) {
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return clz64_impl_c(x);
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}
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static really_inline
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u32 ctz32_impl(u32 x) {
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return ctz32_impl_c(x);
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}
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static really_inline
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u32 ctz64_impl(u64a x) {
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return ctz64_impl_c(x);
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}
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static really_inline
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u32 lg2_impl(u32 x) {
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return lg2_impl_c(x);
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}
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static really_inline
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u64a lg2_64_impl(u64a x) {
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return lg2_64_impl_c(x);
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}
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static really_inline
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u32 findAndClearLSB_32_impl(u32 *v) {
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return findAndClearLSB_32_impl_c(v);
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}
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static really_inline
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u32 findAndClearLSB_64_impl(u64a *v) {
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return findAndClearLSB_64_impl_c(v);
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}
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static really_inline
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u32 findAndClearMSB_32_impl(u32 *v) {
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return findAndClearMSB_32_impl_c(v);
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}
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static really_inline
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u32 findAndClearMSB_64_impl(u64a *v) {
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return findAndClearMSB_64_impl_c(v);
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}
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static really_inline
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u32 compress32_impl(u32 x, u32 m) {
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return compress32_impl_c(x, m);
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}
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static really_inline
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u64a compress64_impl(u64a x, u64a m) {
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return compress64_impl_c(x, m);
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}
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static really_inline
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m128 compress128_impl(m128 x, m128 m) {
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m128 one = set1_2x64(1);
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m128 bb = one;
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m128 res = zeroes128();
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while (isnonzero128(m)) {
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m128 mm = sub_2x64(zeroes128(), m);
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m128 xm = and128(x, m);
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xm = and128(xm, mm);
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m128 mask = not128(eq64_m128(xm, zeroes128()));
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res = or128(res, and128(bb, mask));
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m = and128(m, sub_2x64(m, one));
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bb = lshift64_m128(bb, 1);
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}
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return res;
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}
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#if defined(HAVE_SVE2_BITPERM)
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#include "bitutils_sve.h"
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#else
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static really_inline
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u32 expand32_impl(u32 x, u32 m) {
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return expand32_impl_c(x, m);
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}
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static really_inline
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u64a expand64_impl(u64a x, u64a m) {
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return expand64_impl_c(x, m);
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}
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#endif // HAVE_SVE2_BITPERM
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static really_inline
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m128 expand128_impl(m128 x, m128 m) {
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m128 one = set1_2x64(1);
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m128 bb = one;
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m128 res = zeroes128();
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while (isnonzero128(m)) {
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m128 xm = and128(x, bb);
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m128 mm = sub_2x64(zeroes128(), m);
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m128 mask = not128(eq64_m128(xm, zeroes128()));
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mask = and128(mask, and128(m, mm));
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res = or128(res, mask);
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m = and128(m, sub_2x64(m, one));
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bb = lshift64_m128(bb, 1);
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}
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return res;
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}
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/* returns the first set bit after begin (if not ~0U). If no bit is set after
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* begin returns ~0U
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*/
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static really_inline
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u32 bf64_iterate_impl(u64a bitfield, u32 begin) {
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if (begin != ~0U) {
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/* switch off all bits at or below begin. Note: not legal to shift by
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* by size of the datatype or larger. */
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assert(begin <= 63);
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bitfield &= ~((2ULL << begin) - 1);
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}
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if (!bitfield) {
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return ~0U;
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}
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return ctz64_impl(bitfield);
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}
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static really_inline
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char bf64_set_impl(u64a *bitfield, u32 i) {
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return bf64_set_impl_c(bitfield, i);
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}
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static really_inline
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void bf64_unset_impl(u64a *bitfield, u32 i) {
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return bf64_unset_impl_c(bitfield, i);
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}
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static really_inline
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u32 rank_in_mask32_impl(u32 mask, u32 bit) {
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return rank_in_mask32_impl_c(mask, bit);
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}
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static really_inline
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u32 rank_in_mask64_impl(u64a mask, u32 bit) {
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return rank_in_mask64_impl_c(mask, bit);
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}
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static really_inline
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u32 pext32_impl(u32 x, u32 mask) {
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return pext32_impl_c(x, mask);
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}
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static really_inline
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u64a pext64_impl(u64a x, u64a mask) {
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return pext64_impl_c(x, mask);
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}
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/* compilers don't reliably synthesize the 32-bit ANDN instruction here,
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* so we force its generation.
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*/
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static really_inline
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u64a andn_impl(const u32 a, const u8 *b) {
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return andn_impl_c(a, b);
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}
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#endif // BITUTILS_ARCH_LOONGARCH64_H
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