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49eb18ee4f
This optimization is based on the thread https://twitter.com/Danlark1/status/1539344279268691970 and uses shift right and narrow by 4 instruction https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/SHRN--SHRN2--Shift-Right-Narrow--immediate-- To achieve that, I needed to redesign a little movemask into comparemask and have an additional step towards mask iteration. Our benchmarks showed 10-15% improvement on average for long matches.
91 lines
3.6 KiB
C++
91 lines
3.6 KiB
C++
/*
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* Copyright (c) 2015-2017, Intel Corporation
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* Copyright (c) 2020-2021, VectorCamp PC
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* * Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Intel Corporation nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/** \file
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* \brief Naive dynamic shuffles.
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*
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* These are written with the assumption that the provided masks are sparsely
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* populated and never contain more than 32 on bits. Other implementations will
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* be faster and actually correct if these assumptions don't hold true.
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*/
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#ifndef LIMEX_SHUFFLE_HPP
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#define LIMEX_SHUFFLE_HPP
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#include "ue2common.h"
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#include "util/arch.h"
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#include "util/bitutils.h"
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#include "util/unaligned.h"
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#include "util/supervector/supervector.hpp"
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template <u16 S>
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u32 packedExtract(SuperVector<S> s, const SuperVector<S> permute, const SuperVector<S> compare);
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template <>
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really_really_inline
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u32 packedExtract<16>(SuperVector<16> s, const SuperVector<16> permute, const SuperVector<16> compare) {
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SuperVector<16> shuffled = s.pshufb<true>(permute);
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SuperVector<16> compared = shuffled & compare;
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u64a rv = (~compared.eqmask(shuffled)) & 0xffff;
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if (SuperVector<16>::mask_width() != 1) {
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u32 ans = 0;
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for (u32 i = 0; i < 16; ++i) {
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ans |= (rv & (1ull << (i * SuperVector<16>::mask_width()))) >>
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(i * SuperVector<16>::mask_width() - i);
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}
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return ans;
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}
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return (u32)rv;
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}
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template <>
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really_really_inline
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u32 packedExtract<32>(SuperVector<32> s, const SuperVector<32> permute, const SuperVector<32> compare) {
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SuperVector<32> shuffled = s.pshufb<true>(permute);
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SuperVector<32> compared = shuffled & compare;
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// TODO(danlark1): Future ARM support might have a bug.
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u64a rv = (~compared.eqmask(shuffled)) & 0xffffffff;
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return (u32)((rv >> 16) | (rv & 0xffffU));
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}
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template <>
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really_really_inline
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u32 packedExtract<64>(SuperVector<64> s, const SuperVector<64> permute, const SuperVector<64> compare) {
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SuperVector<64> shuffled = s.pshufb<true>(permute);
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SuperVector<64> compared = shuffled & compare;
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// TODO(danlark1): Future ARM support might have a bug.
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u64a rv = ~compared.eqmask(shuffled);
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rv = rv >> 32 | rv;
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return (u32)(((rv >> 16) | rv) & 0xffffU);
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}
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#endif // LIMEX_SHUFFLE_HPP
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