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Make the GPR NFA models only clear cached_estate conditionally based on cached_br, as per the SIMD models.
167 lines
5.4 KiB
C
167 lines
5.4 KiB
C
/*
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* Copyright (c) 2015, Intel Corporation
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* * Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Intel Corporation nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/** \file
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* \brief LimEx NFA: native GPR runtime implementations.
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*/
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//#define DEBUG
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//#define DEBUG_INPUT
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//#define DEBUG_EXCEPTIONS
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#include "limex.h"
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#include "accel.h"
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#include "limex_internal.h"
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#include "nfa_internal.h"
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#include "ue2common.h"
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#include "util/bitutils.h"
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// Common code
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#define STATE_ON_STACK
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#define ESTATE_ON_STACK
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#include "limex_runtime.h"
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// Other implementation code from X-Macro impl.
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#define SIZE 32
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#define STATE_T u32
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#include "limex_state_impl.h"
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#define SIZE 32
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#define STATE_T u32
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#define INLINE_ATTR really_inline
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#include "limex_common_impl.h"
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////////////////////////////////////////////////////////////////////////////
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// LimEx NFA implementation code - general purpose registers
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////////////////////////////////////////////////////////////////////////////
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// Process exceptional states
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#define SIZE 32
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#define STATE_T u32
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#define STATE_ON_STACK
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#define ESTATE_ON_STACK
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#define RUN_EXCEPTION_FN_ONLY
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#include "limex_exceptional.h"
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static really_inline
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int processExceptional32(u32 s, u32 estate, UNUSED u32 diffmask, u32 *succ,
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const struct LimExNFA32 *limex,
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const u32 *exceptionMap,
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const struct NFAException32 *exceptions,
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const ReportID *exReports, u64a offset,
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struct NFAContext32 *ctx, char in_rev, char flags) {
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assert(estate != 0); // guaranteed by calling macro
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if (estate == ctx->cached_estate) {
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DEBUG_PRINTF("using cached succ from previous state\n");
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*succ |= ctx->cached_esucc;
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if (ctx->cached_reports && (flags & CALLBACK_OUTPUT)) {
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DEBUG_PRINTF("firing cached reports from previous state\n");
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if (unlikely(limexRunReports(ctx->cached_reports, ctx->callback,
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ctx->context, offset)
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== MO_HALT_MATCHING)) {
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return PE_RV_HALT; // halt;
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}
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}
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return 0;
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}
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u32 orig_estate = estate; // for caching
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u32 local_succ = 0;
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struct proto_cache new_cache = {0, NULL};
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enum CacheResult cacheable = CACHE_RESULT;
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/* Note that only exception-states that consist of exceptions that _only_
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* set successors (not fire accepts or squash states) are cacheable. */
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do {
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u32 bit = findAndClearLSB_32(&estate);
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u32 idx = exceptionMap[bit];
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const struct NFAException32 *e = &exceptions[idx];
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if (!runException32(e, s, succ, &local_succ, limex, exReports, offset,
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ctx, &new_cache, &cacheable, in_rev, flags)) {
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return PE_RV_HALT;
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}
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} while (estate != 0);
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*succ |= local_succ;
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if (cacheable == CACHE_RESULT) {
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ctx->cached_estate = orig_estate;
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ctx->cached_esucc = local_succ;
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ctx->cached_reports = new_cache.reports;
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ctx->cached_br = new_cache.br;
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} else if (cacheable == DO_NOT_CACHE_RESULT_AND_FLUSH_BR_ENTRIES) {
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if (ctx->cached_br) {
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ctx->cached_estate = 0U;
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}
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}
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return 0;
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}
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// 32-bit models.
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#define SIZE 32
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#define STATE_T u32
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#define SHIFT 1
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#include "limex_runtime_impl.h"
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#define SIZE 32
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#define STATE_T u32
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#define SHIFT 2
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#include "limex_runtime_impl.h"
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#define SIZE 32
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#define STATE_T u32
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#define SHIFT 3
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#include "limex_runtime_impl.h"
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#define SIZE 32
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#define STATE_T u32
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#define SHIFT 4
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#include "limex_runtime_impl.h"
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#define SIZE 32
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#define STATE_T u32
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#define SHIFT 5
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#include "limex_runtime_impl.h"
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#define SIZE 32
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#define STATE_T u32
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#define SHIFT 6
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#include "limex_runtime_impl.h"
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#define SIZE 32
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#define STATE_T u32
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#define SHIFT 7
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#include "limex_runtime_impl.h"
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