github_mirrors/vectorscan
3
0
Fork 1
mirror of https://github.com/VectorCamp/vectorscan.git synced 2025-09-30 19:47:43 +03:00
Code Issues Packages Projects Releases Wiki Activity

nfa: switch to using bytecode_ptr<NFA>

Browse Source
This commit is contained in:
Justin Viiret
2017-04-03 17:21:37 +10:00
committed by Matthew Barr
parent 905ac78061
commit a197074c5d
27 changed files with 251 additions and 241 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
src/nfa/castlecompile.cpp
View File

@@ -26,9 +26,11 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
/** \file
/**
* \file
* \brief Castle: multi-tenant repeat engine, compiler code.
*/
#include "castlecompile.h"
#include "castle_internal.h"
@@ -439,7 +441,7 @@ void buildSubcastles(const CastleProto &proto, vector<SubCastle> &subs,
}
}
aligned_unique_ptr<NFA>
bytecode_ptr<NFA>
buildCastle(const CastleProto &proto,
const map<u32, vector<vector<CharReach>>> &triggers,
const CompileContext &cc, const ReportManager &rm) {
@@ -577,7 +579,7 @@ buildCastle(const CastleProto &proto,
total_size = ROUNDUP_N(total_size, alignof(mmbit_sparse_iter));
total_size += byte_length(stale_iter); // stale sparse iter
aligned_unique_ptr<NFA> nfa = aligned_zmalloc_unique<NFA>(total_size);
auto nfa = make_bytecode_ptr<NFA>(total_size);
nfa->type = verify_u8(CASTLE_NFA);
nfa->length = verify_u32(total_size);
nfa->nPositions = verify_u32(subs.size());

9
src/nfa/castlecompile.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2016, Intel Corporation
* Copyright (c) 2015-2017, Intel Corporation
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -26,7 +26,8 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
/** \file
/**
* \file
* \brief Castle: multi-tenant repeat engine, compiler code.
*/
@@ -36,7 +37,7 @@
#include "nfa_kind.h"
#include "ue2common.h"
#include "nfagraph/ng_repeat.h"
#include "util/alloc.h"
#include "util/bytecode_ptr.h"
#include "util/depth.h"
#include "util/ue2_containers.h"
@@ -120,7 +121,7 @@ void remapCastleTops(CastleProto &proto, std::map<u32, u32> &top_map);
* NOTE: Tops must be contiguous, i.e. \ref remapCastleTops must have been run
* first.
*/
ue2::aligned_unique_ptr<NFA>
bytecode_ptr<NFA>
buildCastle(const CastleProto &proto,
const std::map<u32, std::vector<std::vector<CharReach>>> &triggers,
const CompileContext &cc, const ReportManager &rm);

13
src/nfa/goughcompile.cpp
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2016, Intel Corporation
* Copyright (c) 2015-2017, Intel Corporation
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -35,7 +35,6 @@
#include "grey.h"
#include "mcclellancompile.h"
#include "nfa_internal.h"
#include "util/alloc.h"
#include "util/compile_context.h"
#include "util/container.h"
#include "util/graph_range.h"
@@ -1036,9 +1035,9 @@ void update_accel_prog_offset(const gough_build_strat &gbs,
}
}
aligned_unique_ptr<NFA> goughCompile(raw_som_dfa &raw, u8 somPrecision,
const CompileContext &cc,
const ReportManager &rm) {
bytecode_ptr<NFA> goughCompile(raw_som_dfa &raw, u8 somPrecision,
const CompileContext &cc,
const ReportManager &rm) {
assert(somPrecision == 2 || somPrecision == 4 || somPrecision == 8
|| !cc.streaming);
@@ -1071,7 +1070,7 @@ aligned_unique_ptr<NFA> goughCompile(raw_som_dfa &raw, u8 somPrecision,
map<dstate_id_t, gough_accel_state_info> accel_allowed;
find_allowed_accel_states(*cfg, blocks, &accel_allowed);
gough_build_strat gbs(raw, *cfg, rm, accel_allowed);
aligned_unique_ptr<NFA> basic_dfa = mcclellanCompile_i(raw, gbs, cc);
auto basic_dfa = mcclellanCompile_i(raw, gbs, cc);
assert(basic_dfa);
if (!basic_dfa) {
return nullptr;
@@ -1117,7 +1116,7 @@ aligned_unique_ptr<NFA> goughCompile(raw_som_dfa &raw, u8 somPrecision,
gi.stream_som_loc_width = somPrecision;
u32 gough_size = ROUNDUP_N(curr_offset, 16);
aligned_unique_ptr<NFA> gough_dfa = aligned_zmalloc_unique<NFA>(gough_size);
auto gough_dfa = make_bytecode_ptr<NFA>(gough_size);
memcpy(gough_dfa.get(), basic_dfa.get(), basic_dfa->length);
memcpy((char *)gough_dfa.get() + haig_offset, &gi, sizeof(gi));

12
src/nfa/goughcompile.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2015, Intel Corporation
* Copyright (c) 2015-2017, Intel Corporation
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -32,7 +32,7 @@
#include "mcclellancompile.h"
#include "nfa_kind.h"
#include "ue2common.h"
#include "util/alloc.h"
#include "util/bytecode_ptr.h"
#include "util/ue2_containers.h"
#include "util/order_check.h"
@@ -88,10 +88,10 @@ struct raw_som_dfa : public raw_dfa {
* som */
};
aligned_unique_ptr<NFA> goughCompile(raw_som_dfa &raw, u8 somPrecision,
const CompileContext &cc,
const ReportManager &rm);
bytecode_ptr<NFA> goughCompile(raw_som_dfa &raw, u8 somPrecision,
const CompileContext &cc,
const ReportManager &rm);
} // namespace ue2
#endif
#endif // GOUGHCOMPILE_H

30
src/nfa/limex_compile.cpp
View File

@@ -26,9 +26,11 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
/** \file
/**
* \file
* \brief Main NFA build code.
*/
#include "limex_compile.h"
#include "accel.h"
@@ -2193,7 +2195,7 @@ struct Factory {
}
static
aligned_unique_ptr<NFA> generateNfa(const build_info &args) {
bytecode_ptr<NFA> generateNfa(const build_info &args) {
if (args.num_states > NFATraits<dtype>::maxStates) {
return nullptr;
}
@@ -2295,7 +2297,7 @@ struct Factory {
size_t nfaSize = sizeof(NFA) + offset;
DEBUG_PRINTF("nfa size %zu\n", nfaSize);
auto nfa = aligned_zmalloc_unique<NFA>(nfaSize);
auto nfa = make_bytecode_ptr<NFA>(nfaSize);
assert(nfa); // otherwise we would have thrown std::bad_alloc
implNFA_t *limex = (implNFA_t *)getMutableImplNfa(nfa.get());
@@ -2381,7 +2383,7 @@ struct Factory {
template<NFAEngineType dtype>
struct generateNfa {
static aligned_unique_ptr<NFA> call(const build_info &args) {
static bytecode_ptr<NFA> call(const build_info &args) {
return Factory<dtype>::generateNfa(args);
}
};
@@ -2478,17 +2480,15 @@ u32 max_state(const ue2::unordered_map<NFAVertex, u32> &state_ids) {
return rv;
}
aligned_unique_ptr<NFA> generate(NGHolder &h,
const ue2::unordered_map<NFAVertex, u32> &states,
const vector<BoundedRepeatData> &repeats,
const map<NFAVertex, NFAStateSet> &reportSquashMap,
const map<NFAVertex, NFAStateSet> &squashMap,
const map<u32, set<NFAVertex>> &tops,
const set<NFAVertex> &zombies,
bool do_accel,
bool stateCompression,
u32 hint,
const CompileContext &cc) {
bytecode_ptr<NFA> generate(NGHolder &h,
const ue2::unordered_map<NFAVertex, u32> &states,
const vector<BoundedRepeatData> &repeats,
const map<NFAVertex, NFAStateSet> &reportSquashMap,
const map<NFAVertex, NFAStateSet> &squashMap,
const map<u32, set<NFAVertex>> &tops,
const set<NFAVertex> &zombies, bool do_accel,
bool stateCompression, u32 hint,
const CompileContext &cc) {
const u32 num_states = max_state(states) + 1;
DEBUG_PRINTF("total states: %u\n", num_states);

14
src/nfa/limex_compile.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2016, Intel Corporation
* Copyright (c) 2015-2017, Intel Corporation
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -26,7 +26,8 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
/** \file
/**
* \file
* \brief Main NFA build code.
*/
@@ -37,10 +38,10 @@
#include <memory>
#include <vector>
#include "ue2common.h"
#include "nfagraph/ng_holder.h"
#include "nfagraph/ng_squash.h" // for NFAStateSet
#include "util/alloc.h"
#include "ue2common.h"
#include "util/bytecode_ptr.h"
#include "util/ue2_containers.h"
struct NFA;
@@ -50,7 +51,8 @@ namespace ue2 {
struct BoundedRepeatData;
struct CompileContext;
/** \brief Construct a LimEx NFA from an NGHolder.
/**
* \brief Construct a LimEx NFA from an NGHolder.
*
* \param g Input NFA graph. Must have state IDs assigned.
* \param repeats Bounded repeat information, if any.
@@ -66,7 +68,7 @@ struct CompileContext;
* \return a built NFA, or nullptr if no NFA could be constructed for this
* graph.
*/
aligned_unique_ptr<NFA> generate(NGHolder &g,
bytecode_ptr<NFA> generate(NGHolder &g,
const ue2::unordered_map<NFAVertex, u32> &states,
const std::vector<BoundedRepeatData> &repeats,
const std::map<NFAVertex, NFAStateSet> &reportSquashMap,

33
src/nfa/mcclellancompile.cpp
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2016, Intel Corporation
* Copyright (c) 2015-2017, Intel Corporation
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -456,9 +456,8 @@ bool allocateFSN16(dfa_info &info, dstate_id_t *sherman_base) {
}
static
aligned_unique_ptr<NFA> mcclellanCompile16(dfa_info &info,
const CompileContext &cc,
set<dstate_id_t> *accel_states) {
bytecode_ptr<NFA> mcclellanCompile16(dfa_info &info, const CompileContext &cc,
set<dstate_id_t> *accel_states) {
DEBUG_PRINTF("building mcclellan 16\n");
vector<u32> reports; /* index in ri for the appropriate report list */
@@ -497,7 +496,7 @@ aligned_unique_ptr<NFA> mcclellanCompile16(dfa_info &info,
accel_offset -= sizeof(NFA); /* adj accel offset to be relative to m */
assert(ISALIGNED_N(accel_offset, alignof(union AccelAux)));
aligned_unique_ptr<NFA> nfa = aligned_zmalloc_unique<NFA>(total_size);
auto nfa = make_bytecode_ptr<NFA>(total_size);
char *nfa_base = (char *)nfa.get();
populateBasicInfo(sizeof(u16), info, total_size, aux_offset, accel_offset,
@@ -685,9 +684,8 @@ void allocateFSN8(dfa_info &info,
}
static
aligned_unique_ptr<NFA> mcclellanCompile8(dfa_info &info,
const CompileContext &cc,
set<dstate_id_t> *accel_states) {
bytecode_ptr<NFA> mcclellanCompile8(dfa_info &info, const CompileContext &cc,
set<dstate_id_t> *accel_states) {
DEBUG_PRINTF("building mcclellan 8\n");
vector<u32> reports;
@@ -717,12 +715,13 @@ aligned_unique_ptr<NFA> mcclellanCompile8(dfa_info &info,
accel_offset -= sizeof(NFA); /* adj accel offset to be relative to m */
assert(ISALIGNED_N(accel_offset, alignof(union AccelAux)));
aligned_unique_ptr<NFA> nfa = aligned_zmalloc_unique<NFA>(total_size);
auto nfa = bytecode_ptr<NFA>(total_size);
char *nfa_base = (char *)nfa.get();
mcclellan *m = (mcclellan *)getMutableImplNfa(nfa.get());
allocateFSN8(info, accel_escape_info, &m->accel_limit_8, &m->accept_limit_8);
allocateFSN8(info, accel_escape_info, &m->accel_limit_8,
&m->accept_limit_8);
populateBasicInfo(sizeof(u8), info, total_size, aux_offset, accel_offset,
accel_escape_info.size(), arb, single, nfa.get());
@@ -939,9 +938,9 @@ bool is_cyclic_near(const raw_dfa &raw, dstate_id_t root) {
return false;
}
aligned_unique_ptr<NFA> mcclellanCompile_i(raw_dfa &raw, accel_dfa_build_strat &strat,
const CompileContext &cc,
set<dstate_id_t> *accel_states) {
bytecode_ptr<NFA> mcclellanCompile_i(raw_dfa &raw, accel_dfa_build_strat &strat,
const CompileContext &cc,
set<dstate_id_t> *accel_states) {
u16 total_daddy = 0;
dfa_info info(strat);
bool using8bit = cc.grey.allowMcClellan8 && info.size() <= 256;
@@ -965,7 +964,7 @@ aligned_unique_ptr<NFA> mcclellanCompile_i(raw_dfa &raw, accel_dfa_build_strat &
info.size() * info.impl_alpha_size, info.size(),
info.impl_alpha_size);
aligned_unique_ptr<NFA> nfa;
bytecode_ptr<NFA> nfa;
if (!using8bit) {
nfa = mcclellanCompile16(info, cc, accel_states);
} else {
@@ -980,9 +979,9 @@ aligned_unique_ptr<NFA> mcclellanCompile_i(raw_dfa &raw, accel_dfa_build_strat &
return nfa;
}
aligned_unique_ptr<NFA> mcclellanCompile(raw_dfa &raw, const CompileContext &cc,
const ReportManager &rm,
set<dstate_id_t> *accel_states) {
bytecode_ptr<NFA> mcclellanCompile(raw_dfa &raw, const CompileContext &cc,
const ReportManager &rm,
set<dstate_id_t> *accel_states) {
mcclellan_build_strat mbs(raw, rm);
return mcclellanCompile_i(raw, mbs, cc, accel_states);
}

12
src/nfa/mcclellancompile.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2016, Intel Corporation
* Copyright (c) 2015-2017, Intel Corporation
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -32,7 +32,7 @@
#include "accel_dfa_build_strat.h"
#include "rdfa.h"
#include "ue2common.h"
#include "util/alloc.h"
#include "util/bytecode_ptr.h"
#include "util/ue2_containers.h"
#include <memory>
@@ -55,7 +55,7 @@ public:
std::vector<u32> &reports /* out */,
std::vector<u32> &reports_eod /* out */,
u8 *isSingleReport /* out */,
ReportID *arbReport /* out */) const override;
ReportID *arbReport /* out */) const override;
size_t accelSize(void) const override;
u32 max_allowed_offset_accel() const override;
u32 max_stop_char() const override;
@@ -67,13 +67,13 @@ private:
/* accel_states: (optional) on success, is filled with the set of accelerable
* states */
ue2::aligned_unique_ptr<NFA>
bytecode_ptr<NFA>
mcclellanCompile(raw_dfa &raw, const CompileContext &cc,
const ReportManager &rm,
std::set<dstate_id_t> *accel_states = nullptr);
/* used internally by mcclellan/haig/gough compile process */
ue2::aligned_unique_ptr<NFA>
bytecode_ptr<NFA>
mcclellanCompile_i(raw_dfa &raw, accel_dfa_build_strat &strat,
const CompileContext &cc,
std::set<dstate_id_t> *accel_states = nullptr);
@@ -89,4 +89,4 @@ bool has_accel_mcclellan(const NFA *nfa);
} // namespace ue2
#endif
#endif // MCCLELLANCOMPILE_H

16
src/nfa/mcsheng_compile.cpp
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016, Intel Corporation
* Copyright (c) 2016-2017, Intel Corporation
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -821,7 +821,7 @@ void fill_in_sherman(NFA *nfa, dfa_info &info, UNUSED u16 sherman_limit) {
}
static
aligned_unique_ptr<NFA> mcshengCompile16(dfa_info &info, dstate_id_t sheng_end,
bytecode_ptr<NFA> mcshengCompile16(dfa_info &info, dstate_id_t sheng_end,
const map<dstate_id_t, AccelScheme> &accel_escape_info,
const Grey &grey) {
DEBUG_PRINTF("building mcsheng 16\n");
@@ -872,7 +872,7 @@ aligned_unique_ptr<NFA> mcshengCompile16(dfa_info &info, dstate_id_t sheng_end,
accel_offset -= sizeof(NFA); /* adj accel offset to be relative to m */
assert(ISALIGNED_N(accel_offset, alignof(union AccelAux)));
aligned_unique_ptr<NFA> nfa = aligned_zmalloc_unique<NFA>(total_size);
auto nfa = make_bytecode_ptr<NFA>(total_size);
mcsheng *m = (mcsheng *)getMutableImplNfa(nfa.get());
populateBasicInfo(sizeof(u16), info, total_size, aux_offset, accel_offset,
@@ -967,7 +967,7 @@ void allocateImplId8(dfa_info &info, dstate_id_t sheng_end,
}
static
aligned_unique_ptr<NFA> mcshengCompile8(dfa_info &info, dstate_id_t sheng_end,
bytecode_ptr<NFA> mcshengCompile8(dfa_info &info, dstate_id_t sheng_end,
const map<dstate_id_t, AccelScheme> &accel_escape_info) {
DEBUG_PRINTF("building mcsheng 8\n");
@@ -998,7 +998,7 @@ aligned_unique_ptr<NFA> mcshengCompile8(dfa_info &info, dstate_id_t sheng_end,
accel_offset -= sizeof(NFA); /* adj accel offset to be relative to m */
assert(ISALIGNED_N(accel_offset, alignof(union AccelAux)));
aligned_unique_ptr<NFA> nfa = aligned_zmalloc_unique<NFA>(total_size);
auto nfa = make_bytecode_ptr<NFA>(total_size);
mcsheng *m = (mcsheng *)getMutableImplNfa(nfa.get());
allocateImplId8(info, sheng_end, accel_escape_info, &m->accel_limit_8,
@@ -1019,8 +1019,8 @@ aligned_unique_ptr<NFA> mcshengCompile8(dfa_info &info, dstate_id_t sheng_end,
return nfa;
}
aligned_unique_ptr<NFA> mcshengCompile(raw_dfa &raw, const CompileContext &cc,
const ReportManager &rm) {
bytecode_ptr<NFA> mcshengCompile(raw_dfa &raw, const CompileContext &cc,
const ReportManager &rm) {
if (!cc.grey.allowMcSheng) {
return nullptr;
}
@@ -1044,7 +1044,7 @@ aligned_unique_ptr<NFA> mcshengCompile(raw_dfa &raw, const CompileContext &cc,
return nullptr;
}
aligned_unique_ptr<NFA> nfa;
bytecode_ptr<NFA> nfa;
if (!using8bit) {
nfa = mcshengCompile16(info, sheng_end, accel_escape_info, cc.grey);
} else {

15
src/nfa/mcsheng_compile.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016, Intel Corporation
* Copyright (c) 2016-2017, Intel Corporation
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -29,13 +29,8 @@
#ifndef MCSHENGCOMPILE_H
#define MCSHENGCOMPILE_H
#include "accel_dfa_build_strat.h"
#include "rdfa.h"
#include "ue2common.h"
#include "util/alloc.h"
#include "util/ue2_containers.h"
#include <memory>
#include "util/bytecode_ptr.h"
struct NFA;
@@ -43,10 +38,10 @@ namespace ue2 {
class ReportManager;
struct CompileContext;
struct raw_dfa;
ue2::aligned_unique_ptr<NFA>
mcshengCompile(raw_dfa &raw, const CompileContext &cc,
const ReportManager &rm);
bytecode_ptr<NFA> mcshengCompile(raw_dfa &raw, const CompileContext &cc,
const ReportManager &rm);
bool has_accel_mcsheng(const NFA *nfa);

11
src/nfa/shengcompile.cpp
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016, Intel Corporation
* Copyright (c) 2016-2017, Intel Corporation
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -450,10 +450,9 @@ bool has_accel_sheng(const NFA *) {
return true; /* consider the sheng region as accelerated */
}
aligned_unique_ptr<NFA> shengCompile(raw_dfa &raw,
const CompileContext &cc,
const ReportManager &rm,
set<dstate_id_t> *accel_states) {
bytecode_ptr<NFA> shengCompile(raw_dfa &raw, const CompileContext &cc,
const ReportManager &rm,
set<dstate_id_t> *accel_states) {
if (!cc.grey.allowSheng) {
DEBUG_PRINTF("Sheng is not allowed!\n");
return nullptr;
@@ -508,7 +507,7 @@ aligned_unique_ptr<NFA> shengCompile(raw_dfa &raw,
DEBUG_PRINTF("NFA: %u, aux: %u, reports: %u, accel: %u, total: %u\n",
nfa_size, total_aux, total_reports, total_accel, total_size);
aligned_unique_ptr<NFA> nfa = aligned_zmalloc_unique<NFA>(total_size);
auto nfa = make_bytecode_ptr<NFA>(total_size);
populateBasicInfo(nfa.get(), info, accelInfo, nfa_size, reports_offset,
accel_offset, total_size, total_size - sizeof(NFA));

16
src/nfa/shengcompile.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016, Intel Corporation
* Copyright (c) 2016-2017, Intel Corporation
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -26,12 +26,12 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef SHENGCOMPILE_H_
#define SHENGCOMPILE_H_
#ifndef SHENGCOMPILE_H
#define SHENGCOMPILE_H
#include "accel_dfa_build_strat.h"
#include "rdfa.h"
#include "util/alloc.h"
#include "util/bytecode_ptr.h"
#include "util/charreach.h"
#include "util/ue2_containers.h"
@@ -62,9 +62,9 @@ private:
raw_dfa &rdfa;
};
aligned_unique_ptr<NFA>
shengCompile(raw_dfa &raw, const CompileContext &cc, const ReportManager &rm,
std::set<dstate_id_t> *accel_states = nullptr);
bytecode_ptr<NFA> shengCompile(raw_dfa &raw, const CompileContext &cc,
const ReportManager &rm,
std::set<dstate_id_t> *accel_states = nullptr);
struct sheng_escape_info {
CharReach outs;
@@ -77,4 +77,4 @@ bool has_accel_sheng(const NFA *nfa);
} // namespace ue2
#endif /* SHENGCOMPILE_H_ */
#endif /* SHENGCOMPILE_H */

17
src/nfa/tamaramacompile.cpp
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016, Intel Corporation
* Copyright (c) 2016-2017, Intel Corporation
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -26,9 +26,9 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
/** \file
* \brief Tamarama: container engine for exclusive engines,
* compiler code.
/**
* \file
* \brief Tamarama: container engine for exclusive engines, compiler code.
*/
#include "config.h"
@@ -111,8 +111,9 @@ void copyInSubnfas(const char *base_offset, NFA &nfa,
* returns via out_top_remap, a mapping indicating how tops in the subengines in
* relate to the tamarama's tops.
*/
aligned_unique_ptr<NFA> buildTamarama(const TamaInfo &tamaInfo, const u32 queue,
map<pair<const NFA *, u32>, u32> &out_top_remap) {
bytecode_ptr<NFA>
buildTamarama(const TamaInfo &tamaInfo, const u32 queue,
map<pair<const NFA *, u32>, u32> &out_top_remap) {
vector<u32> top_base;
remapTops(tamaInfo, top_base, out_top_remap);
@@ -133,7 +134,7 @@ aligned_unique_ptr<NFA> buildTamarama(const TamaInfo &tamaInfo, const u32 queue,
// use subSize as a sentinel value for no active subengines,
// so add one to subSize here
u32 activeIdxSize = calcPackedBytes(subSize + 1);
aligned_unique_ptr<NFA> nfa = aligned_zmalloc_unique<NFA>(total_size);
auto nfa = make_bytecode_ptr<NFA>(total_size);
nfa->type = verify_u8(TAMARAMA_NFA);
nfa->length = verify_u32(total_size);
nfa->queueIndex = queue;
@@ -148,7 +149,7 @@ aligned_unique_ptr<NFA> buildTamarama(const TamaInfo &tamaInfo, const u32 queue,
copy_bytes(ptr, top_base);
ptr += byte_length(top_base);
u32 *offsets = (u32*)ptr;
u32 *offsets = (u32 *)ptr;
char *sub_nfa_offset = ptr + sizeof(u32) * subSize;
copyInSubnfas(base_offset, *nfa, tamaInfo, offsets, sub_nfa_offset,
activeIdxSize);

22
src/nfa/tamaramacompile.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016, Intel Corporation
* Copyright (c) 2016-2017, Intel Corporation
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -26,15 +26,16 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
/** \file
* \brief Tamarama: container engine for exclusive engines, compiler code.
/**
* \file
* \brief Tamarama: container engine for exclusive engines, compiler code.
*/
#ifndef NFA_TAMARAMACOMPILE_H
#define NFA_TAMARAMACOMPILE_H
#include "ue2common.h"
#include "util/alloc.h"
#include "util/bytecode_ptr.h"
#include <map>
#include <set>
@@ -45,7 +46,7 @@ struct NFA;
namespace ue2 {
/**
* \brief A TamaProto that contains top remapping and reports info
* \brief A TamaProto that contains top remapping and reports info.
*/
struct TamaProto {
void add(const NFA *n, const u32 id, const u32 top,
@@ -59,7 +60,7 @@ struct TamaProto {
};
/**
* \brief Contruction info for a Tamarama engine:
* \brief Construction info for a Tamarama engine:
* contains at least two subengines.
*
* A TamaInfo is converted into a single NFA, with each top triggering a
@@ -70,7 +71,7 @@ struct TamaInfo {
static constexpr size_t max_occupancy = 65536; // arbitrary limit
/** \brief Add a new subengine. */
void add(NFA* sub, const std::set<u32> &top);
void add(NFA *sub, const std::set<u32> &top);
/** \brief All the subengines */
std::vector<NFA *> subengines;
@@ -86,9 +87,10 @@ std::set<ReportID> all_reports(const TamaProto &proto);
* returns via out_top_remap, a mapping indicating how tops in the subengines in
* relate to the tamarama's tops.
*/
ue2::aligned_unique_ptr<NFA> buildTamarama(const TamaInfo &tamaInfo,
const u32 queue,
std::map<std::pair<const NFA *, u32>, u32> &out_top_remap);
bytecode_ptr<NFA>
buildTamarama(const TamaInfo &tamaInfo, const u32 queue,
std::map<std::pair<const NFA *, u32>, u32> &out_top_remap);
} // namespace ue2
#endif // NFA_TAMARAMACOMPILE_H