Introduce a 64-bit LimEx model.

On 64-bit platforms, the Limex 64 model is implemented in normal GPRs.
On 32-bit platforms, however, 128-bit SSE registers are used for the
runtime implementation.

unit/internal/limex_nfa.cpp

@@ -31,7 +31,6 @@
 
 #include "grey.h"
 #include "compiler/compiler.h"
-#include "nfa/limex_context.h"
 #include "nfa/limex_internal.h"
 #include "nfa/nfa_api.h"
 #include "nfa/nfa_api_util.h"
@@ -167,11 +166,10 @@ TEST_P(LimExModelTest, QueueExec) {
 TEST_P(LimExModelTest, CompressExpand) {
     ASSERT_TRUE(nfa != nullptr);
 
-    // 64-bit NFAs assume during compression that they have >= 5 bytes of
-    // compressed NFA state, which isn't true for our 8-state test pattern. We
-    // skip this test for just these models.
-    if (nfa->scratchStateSize == 8) {
-        return;
+    u32 real_state_size = nfa->scratchStateSize;
+    /* Only look at 8 bytes for limex 64 (rather than the padding) */
+    if (nfa->type == LIMEX_NFA_64) {
+        real_state_size = sizeof(u64a);
     }
 
     initQueue();
@@ -195,8 +193,7 @@ TEST_P(LimExModelTest, CompressExpand) {
     memset(dest, 0xff, nfa->scratchStateSize);
     nfaExpandState(nfa.get(), dest, q.streamState, q.offset,
                    queue_prev_byte(&q, end));
-    ASSERT_TRUE(std::equal(dest, dest + nfa->scratchStateSize,
-                           full_state.get()));
+    ASSERT_TRUE(std::equal(dest, dest + real_state_size, full_state.get()));
 }
 
 TEST_P(LimExModelTest, InitCompressedState0) {

unit/internal/simd_utils.cpp

@@ -110,10 +110,10 @@ void simd_setbit(m128 *a, unsigned int i) { return setbit128(a, i); }
 void simd_setbit(m256 *a, unsigned int i) { return setbit256(a, i); }
 void simd_setbit(m384 *a, unsigned int i) { return setbit384(a, i); }
 void simd_setbit(m512 *a, unsigned int i) { return setbit512(a, i); }
-bool simd_testbit(const m128 *a, unsigned int i) { return testbit128(a, i); }
-bool simd_testbit(const m256 *a, unsigned int i) { return testbit256(a, i); }
-bool simd_testbit(const m384 *a, unsigned int i) { return testbit384(a, i); }
-bool simd_testbit(const m512 *a, unsigned int i) { return testbit512(a, i); }
+bool simd_testbit(const m128 &a, unsigned int i) { return testbit128(a, i); }
+bool simd_testbit(const m256 &a, unsigned int i) { return testbit256(a, i); }
+bool simd_testbit(const m384 &a, unsigned int i) { return testbit384(a, i); }
+bool simd_testbit(const m512 &a, unsigned int i) { return testbit512(a, i); }
 u32 simd_diffrich(const m128 &a, const m128 &b) { return diffrich128(a, b); }
 u32 simd_diffrich(const m256 &a, const m256 &b) { return diffrich256(a, b); }
 u32 simd_diffrich(const m384 &a, const m384 &b) { return diffrich384(a, b); }
@@ -419,15 +419,15 @@ TYPED_TEST(SimdUtilsTest, testbit) {
 
     // First, all bits are on in 'ones'.
     for (unsigned int i = 0; i < total_bits; i++) {
-        ASSERT_EQ(1, simd_testbit(&ones, i)) << "bit " << i << " is on";
+        ASSERT_EQ(1, simd_testbit(ones, i)) << "bit " << i << " is on";
     }
 
     // Try individual bits; only 'i' should be on.
     for (unsigned int i = 0; i < total_bits; i++) {
         TypeParam a = setbit<TypeParam>(i);
         for (unsigned int j = 0; j < total_bits; j++) {
-            ASSERT_EQ(i == j ? 1 : 0, simd_testbit(&a, j)) << "bit " << i
-                                                           << " is wrong";
+            ASSERT_EQ(i == j ? 1 : 0, simd_testbit(a, j)) << "bit " << i
+                                                          << " is wrong";
         }
     }
 }
@@ -470,7 +470,7 @@ TYPED_TEST(SimdUtilsTest, diffrich) {
 
     // and nothing is on in zeroes
     for (unsigned int i = 0; i < total_bits; i++) {
-        ASSERT_EQ(0, simd_testbit(&zeroes, i)) << "bit " << i << " is off";
+        ASSERT_EQ(0, simd_testbit(zeroes, i)) << "bit " << i << " is off";
     }
 
     // All-zeroes and all-ones differ in all words

unit/internal/uniform_ops.cpp

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015, Intel Corporation
+ * Copyright (c) 2015-2016, Intel Corporation
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -156,26 +156,26 @@ TEST(Uniform, loadstore_m512) {
 TEST(Uniform, testbit_u32) {
     for (u32 i = 0; i < 32; i++) {
         u32 v = 0;
-        EXPECT_EQ((char)0, testbit_u32(&v, i));
+        EXPECT_EQ((char)0, testbit_u32(v, i));
         v |= 1ULL << i;
-        EXPECT_EQ((char)1, testbit_u32(&v, i));
+        EXPECT_EQ((char)1, testbit_u32(v, i));
         v = ~v;
-        EXPECT_EQ((char)0, testbit_u32(&v, i));
+        EXPECT_EQ((char)0, testbit_u32(v, i));
         v |= 1ULL << i;
-        EXPECT_EQ((char)1, testbit_u32(&v, i));
+        EXPECT_EQ((char)1, testbit_u32(v, i));
     }
 }
 
 TEST(Uniform, testbit_u64a) {
     for (u32 i = 0; i < 64; i++) {
         u64a v = 0;
-        EXPECT_EQ((char)0, testbit_u64a(&v, i));
+        EXPECT_EQ((char)0, testbit_u64a(v, i));
         v |= 1ULL << i;
-        EXPECT_EQ((char)1, testbit_u64a(&v, i));
+        EXPECT_EQ((char)1, testbit_u64a(v, i));
         v = ~v;
-        EXPECT_EQ((char)0, testbit_u64a(&v, i));
+        EXPECT_EQ((char)0, testbit_u64a(v, i));
         v |= 1ULL << i;
-        EXPECT_EQ((char)1, testbit_u64a(&v, i));
+        EXPECT_EQ((char)1, testbit_u64a(v, i));
     }
 }
 
@@ -183,7 +183,7 @@ TEST(Uniform, clearbit_u32) {
     for (u32 i = 0; i < 32; i++) {
         u32 v = ~0U;
         clearbit_u32(&v, i);
-        EXPECT_EQ((char)0, testbit_u32(&v, i));
+        EXPECT_EQ((char)0, testbit_u32(v, i));
         v = ~v;
         clearbit_u32(&v, i);
         EXPECT_EQ(0U, v);
@@ -194,7 +194,7 @@ TEST(Uniform, clearbit_u64a) {
     for (u32 i = 0; i < 64; i++) {
         u64a v = ~0ULL;
         clearbit_u64a(&v, i);
-        EXPECT_EQ((char)0, testbit_u64a(&v, i));
+        EXPECT_EQ((char)0, testbit_u64a(v, i));
         v = ~v;
         clearbit_u64a(&v, i);
         EXPECT_EQ(0ULL, v);