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Initial commit of Hyperscan
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src/fdr/fdr_engine_description.cpp
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216
src/fdr/fdr_engine_description.cpp
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/*
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* Copyright (c) 2015, Intel Corporation
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* * Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Intel Corporation nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "fdr_compile_internal.h"
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#include "fdr_engine_description.h"
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#include "hs_compile.h"
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#include "util/target_info.h"
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#include "util/compare.h" // for ourisalpha()
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#include "util/make_unique.h"
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#include <cassert>
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#include <cstdlib>
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#include <map>
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#include <string>
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using namespace std;
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namespace ue2 {
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#include "fdr_autogen_compiler.cpp"
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FDREngineDescription::FDREngineDescription(const FDREngineDef &def)
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: EngineDescription(def.id, targetByArchFeatures(def.cpu_features),
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def.numBuckets, def.confirmPullBackDistance,
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def.confirmTopLevelSplit),
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schemeWidth(def.schemeWidth), stride(def.stride), bits(def.bits) {}
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u32 FDREngineDescription::getDefaultFloodSuffixLength() const {
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// rounding up, so that scheme width 32 and 6 buckets is 6 not 5!
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// the +1 avoids pain due to various reach choices
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return ((getSchemeWidth() + getNumBuckets() - 1) / getNumBuckets()) + 1;
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}
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static
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u32 findDesiredStride(size_t num_lits, size_t min_len, size_t min_len_count) {
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u32 desiredStride = 1; // always our safe fallback
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if (min_len > 1) {
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if (num_lits < 250) {
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// small cases we just go for it
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desiredStride = min_len;
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} else if (num_lits < 800) {
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// intermediate cases
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desiredStride = min_len - 1;
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} else if (num_lits < 5000) {
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// for larger but not huge sizes, go to stride 2 only if we have at
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// least minlen 3
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desiredStride = MIN(min_len - 1, 2);
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}
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}
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// patch if count is quite large - a ton of length 2 literals can
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// break things
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#ifdef TRY_THIS_LATER
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if ((min_len == 2) && (desiredStride == 2) && (min_len_count > 20)) {
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desiredStride = 1;
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}
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#endif
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// patch stuff just for the stride 4 case; don't let min_len=4,
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// desiredStride=4 through as even a few length 4 literals can break things
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// (far more fragile)
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if ((min_len == 4) && (desiredStride == 4) && (min_len_count > 2)) {
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desiredStride = 2;
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}
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return desiredStride;
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}
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unique_ptr<FDREngineDescription> chooseEngine(const target_t &target,
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const vector<hwlmLiteral> &vl,
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bool make_small) {
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vector<FDREngineDescription> allDescs;
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getFdrDescriptions(&allDescs);
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// find desired stride
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size_t count;
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size_t msl = minLenCount(vl, &count);
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u32 desiredStride = findDesiredStride(vl.size(), msl, count);
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DEBUG_PRINTF("%zu lits, msl=%zu, desiredStride=%u\n", vl.size(), msl,
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desiredStride);
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const FDREngineDescription *best = nullptr;
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u32 best_score = 0;
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for (size_t engineID = 0; engineID < allDescs.size(); engineID++) {
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const FDREngineDescription &eng = allDescs[engineID];
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if (!eng.isValidOnTarget(target)) {
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continue;
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}
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if (msl < eng.stride) {
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continue;
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}
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u32 score = 100;
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score -= absdiff(desiredStride, eng.stride);
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if (eng.stride <= desiredStride) {
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score += eng.stride;
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}
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u32 effLits = vl.size(); /* * desiredStride;*/
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u32 ideal;
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if (effLits < eng.getNumBuckets()) {
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if (eng.stride == 1) {
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ideal = 8;
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} else {
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ideal = 10;
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}
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} else if (effLits < 20) {
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ideal = 10;
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} else if (effLits < 100) {
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ideal = 11;
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} else if (effLits < 1000) {
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ideal = 12;
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} else if (effLits < 10000) {
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ideal = 13;
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} else {
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ideal = 15;
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}
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if (ideal != 8 && eng.schemeWidth == 32) {
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ideal += 1;
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}
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if (make_small) {
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ideal -= 2;
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}
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if (eng.stride > 1) {
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ideal++;
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}
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DEBUG_PRINTF("effLits %u\n", effLits);
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if (target.is_atom_class() && !make_small && effLits < 4000) {
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/* Unless it is a very heavy case, we want to build smaller tables
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* on lightweight machines due to their small caches. */
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ideal -= 2;
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}
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score -= absdiff(ideal, eng.bits);
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DEBUG_PRINTF("fdr %u: width=%u, bits=%u, buckets=%u, stride=%u "
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"-> score=%u\n",
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eng.getID(), eng.schemeWidth, eng.bits,
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eng.getNumBuckets(), eng.stride, score);
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if (!best || score > best_score) {
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best = ŋ
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best_score = score;
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}
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}
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if (!best) {
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DEBUG_PRINTF("failed to find engine\n");
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return nullptr;
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}
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DEBUG_PRINTF("using engine %u\n", best->getID());
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return ue2::make_unique<FDREngineDescription>(*best);
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}
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SchemeBitIndex FDREngineDescription::getSchemeBit(BucketIndex b,
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PositionInBucket p) const {
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assert(p < getBucketWidth(b));
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SchemeBitIndex sbi = p * getNumBuckets() + b;
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assert(sbi < getSchemeWidth());
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return sbi;
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}
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u32 FDREngineDescription::getBucketWidth(BucketIndex) const {
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u32 sw = getSchemeWidth();
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u32 nm = getNumBuckets();
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assert(sw % nm == 0);
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return sw/nm;
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}
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unique_ptr<FDREngineDescription> getFdrDescription(u32 engineID) {
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vector<FDREngineDescription> allDescs;
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getFdrDescriptions(&allDescs);
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if (engineID >= allDescs.size()) {
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return nullptr;
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}
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return ue2::make_unique<FDREngineDescription>(allDescs[engineID]);
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}
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} // namespace ue2
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