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https://github.com/VectorCamp/vectorscan.git
synced 2025-09-29 19:24:25 +03:00
Check compiler architecture flags in one place
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2015-2016, Intel Corporation
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* Copyright (c) 2015-2017, Intel Corporation
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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@@ -29,6 +29,7 @@
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#include "config.h"
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#include "gtest/gtest.h"
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#include "util/arch.h"
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#include "util/bitutils.h"
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#include "util/popcount.h"
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@@ -437,7 +438,7 @@ TEST(BitUtils, rank_in_mask64) {
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ASSERT_EQ(31, rank_in_mask64(0xf0f0f0f0f0f0f0f0ULL, 63));
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}
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#if defined(HAVE_PEXT) && defined(ARCH_64_BIT)
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#if defined(HAVE_BMI2) && defined(ARCH_64_BIT)
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TEST(BitUtils, pdep64) {
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u64a data = 0xF123456789ABCDEF;
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ASSERT_EQ(0xfULL, pdep64(data, 0xf));
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2015, Intel Corporation
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* Copyright (c) 2015-2017, Intel Corporation
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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@@ -33,6 +33,7 @@
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#include "crc32.h"
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#include "database.h"
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#include "ue2common.h"
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#include "util/arch.h"
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#include "util/target_info.h"
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#include "gtest/gtest.h"
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@@ -47,7 +48,7 @@ TEST(DB, flagsToPlatform) {
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p.cpu_features = 0;
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#if defined(__AVX2__)
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#if defined(HAVE_AVX2)
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p.cpu_features |= HS_CPU_FEATURES_AVX2;
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#endif
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2015, Intel Corporation
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* Copyright (c) 2015-2017, Intel Corporation
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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@@ -31,11 +31,12 @@
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#include <cstring>
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#include "gtest/gtest.h"
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#include "util/arch.h"
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#include "util/masked_move.h"
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namespace {
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#if defined(__AVX2__)
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#if defined(HAVE_AVX2)
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bool try_mask_len(const u8 *buf, u8 *target, size_t len) {
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memset(target, 0, 32);
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2015-2016, Intel Corporation
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* Copyright (c) 2015-2017, Intel Corporation
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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@@ -30,6 +30,7 @@
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#include "gtest/gtest.h"
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#include "util/arch.h"
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#include "util/simd_utils.h"
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#include "nfa/limex_shuffle.h"
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@@ -194,7 +195,7 @@ TEST(Shuffle, PackedExtract128_1) {
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}
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}
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#if defined(__AVX2__)
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#if defined(HAVE_AVX2)
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TEST(Shuffle, PackedExtract256_1) {
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// Try all possible one-bit masks
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for (unsigned int i = 0; i < 256; i++) {
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2015-2016, Intel Corporation
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* Copyright (c) 2015-2017, Intel Corporation
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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@@ -30,6 +30,7 @@
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#include "gtest/gtest.h"
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#include "util/alloc.h"
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#include "util/arch.h"
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#include "util/make_unique.h"
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#include "util/simd_utils.h"
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@@ -620,7 +621,7 @@ TEST(SimdUtilsTest, set4x32) {
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ASSERT_EQ(0, memcmp(cmp, &simd, sizeof(simd)));
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}
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#if defined(__AVX2__)
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#if defined(HAVE_AVX2)
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TEST(SimdUtilsTest, set32x8) {
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char cmp[sizeof(m256)];
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