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https://github.com/VectorCamp/vectorscan.git
synced 2025-11-19 02:30:35 +03:00
update powerpc simd util file functions
This commit is contained in:
apostolos
@@ -61,7 +61,9 @@ static really_inline m128 zeroes128(void) {
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/** \brief Bitwise not for m128*/
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static really_inline m128 not128(m128 a) {
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return (m128) vec_xor(a, a);
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return (m128)vec_xor(a, ones128());
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// or
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return (m128)vec_xor(a, a);
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}
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/** \brief Return 1 if a and b are different otherwise 0 */
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@@ -70,7 +72,7 @@ static really_inline int diff128(m128 a, m128 b) {
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}
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static really_inline int isnonzero128(m128 a) {
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return diff128(a, zeroes128());
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return !!diff128(a, zeroes128());
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}
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/**
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@@ -115,74 +117,95 @@ m128 sub_2x64(m128 a, m128 b) {
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static really_really_inline
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m128 lshift_m128(m128 a, unsigned b) {
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return (m128) vshlq_n_s32((int64x2_t)a, b);
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//return (m128) vshlq_n_s32((int64x2_t)a, b);
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return (m128) vec_sl((int64x2_t)a, b);
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// or
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// return (m128) vec_sll((int64x2_t)a, b);
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// the above command executes Left shifts an entire vector by a given number of bits.
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}
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static really_really_inline
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m128 rshift_m128(m128 a, unsigned b) {
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return (m128) vshrq_n_s32((int64x2_t)a, b);
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//return (m128) vshrq_n_s32((int64x2_t)a, b);
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return (m128) vec_srl((int64x2_t)a, b);
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// or
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// return (m128) vec_srl((int64x2_t)a, b);
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// the above command executes Right shifts an entire vector by a given number of bits.
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}
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static really_really_inline
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m128 lshift64_m128(m128 a, unsigned b) {
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return (m128) vshlq_n_s64((int64x2_t)a, b);
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return (m128) vec_sldw ((int64x2_t)a, b, 8);
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}
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static really_really_inline
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m128 rshift64_m128(m128 a, unsigned b) {
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return (m128) vshrq_n_s64((int64x2_t)a, b);
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//return (m128) vshrq_n_s64((int64x2_t)a, b);
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#warning FIXME
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}
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static really_inline m128 eq128(m128 a, m128 b) {
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return (m128) vceqq_s8((int8x16_t)a, (int8x16_t)b);
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return (m128) vec_all_eq((uint64x2_t)a, (uint64x2_t)b);
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//or
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//return (m128) vec_cmpeq((uint64x2_t)a, (uint64x2_t)b);
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}
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static really_inline m128 eq64_m128(m128 a, m128 b) {
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return (m128) vceqq_u64((int64x2_t)a, (int64x2_t)b);
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//return (m128) vceqq_u64((int64x2_t)a, (int64x2_t)b);
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#warning FIXME
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}
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static really_inline u32 movemask128(m128 a) {
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static const uint8x16_t powers = { 1, 2, 4, 8, 16, 32, 64, 128, 1, 2, 4, 8, 16, 32, 64, 128 };
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//static const uint8x16_t powers = { 1, 2, 4, 8, 16, 32, 64, 128, 1, 2, 4, 8, 16, 32, 64, 128 };
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// Compute the mask from the input
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uint64x2_t mask = vpaddlq_u32(vpaddlq_u16(vpaddlq_u8(vandq_u8((uint8x16_t)a, powers))));
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uint64x2_t mask1 = (m128)vextq_s8(mask, zeroes128(), 7);
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mask = vorrq_u8(mask, mask1);
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//uint64x2_t mask = vpaddlq_u32(vpaddlq_u16(vpaddlq_u8(vandq_u8((uint8x16_t)a, powers))));
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//uint64x2_t mask1 = (m128)vextq_s8(mask, zeroes128(), 7);
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//mask = vorrq_u8(mask, mask1);
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// Get the resulting bytes
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uint16_t output;
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vst1q_lane_u16((uint16_t*)&output, (uint16x8_t)mask, 0);
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return output;
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//uint16_t output;
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//vst1q_lane_u16((uint16_t*)&output, (uint16x8_t)mask, 0);
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//return output;
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#warning FIXME
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}
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static really_inline m128 set1_16x8(u8 c) {
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return (m128) vdupq_n_u8(c);
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//return (m128) vdupq_n_u8(c);
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return (m128) vec_splat_u8(c);
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}
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static really_inline m128 set1_4x32(u32 c) {
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return (m128) vdupq_n_u32(c);
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//return (m128) vdupq_n_u32(c);
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return (m128) vec_splat_u32(c);
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}
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static really_inline m128 set1_2x64(u64a c) {
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return (m128) vdupq_n_u64(c);
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//return (m128) vdupq_n_u64(c);
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return (m128) vec_splat_u64(c);
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}
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static really_inline u32 movd(const m128 in) {
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return vgetq_lane_u32((uint32x4_t) in, 0);
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//return vgetq_lane_u32((uint32x4_t) in, 0);
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#warning FIXME
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}
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static really_inline u64a movq(const m128 in) {
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return vgetq_lane_u64((uint64x2_t) in, 0);
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//return vgetq_lane_u64((uint64x2_t) in, 0);
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#warning FIXME
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}
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/* another form of movq */
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static really_inline
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m128 load_m128_from_u64a(const u64a *p) {
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return (m128) vsetq_lane_u64(*p, zeroes128(), 0);
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//return (m128) vsetq_lane_u64(*p, zeroes128(), 0);
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#warning FIXME
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}
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static really_inline u32 extract32from128(const m128 in, unsigned imm) {
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/*
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#if defined(HS_OPTIMIZE)
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return vgetq_lane_u32((uint32x4_t) in, imm);
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#else
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@@ -204,9 +227,12 @@ static really_inline u32 extract32from128(const m128 in, unsigned imm) {
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break;
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}
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#endif
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*/
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#warning FIXME
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}
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static really_inline u64a extract64from128(const m128 in, unsigned imm) {
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/*
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#if defined(HS_OPTIMIZE)
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return vgetq_lane_u64((uint64x2_t) in, imm);
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#else
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@@ -222,56 +248,70 @@ static really_inline u64a extract64from128(const m128 in, unsigned imm) {
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break;
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}
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#endif
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*/
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#warning FIXME
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}
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static really_inline m128 low64from128(const m128 in) {
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return vcombine_u64(vget_low_u64(in), vdup_n_u64(0));
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//return vcombine_u64(vget_low_u64(in), vdup_n_u64(0));
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#warning FIXME
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}
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static really_inline m128 high64from128(const m128 in) {
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return vcombine_u64(vget_high_u64(in), vdup_n_u64(0));
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//return vcombine_u64(vget_high_u64(in), vdup_n_u64(0));
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#warning FIXME
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}
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static really_inline m128 add128(m128 a, m128 b) {
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return (m128) vaddq_u64((uint64x2_t)a, (uint64x2_t)b);
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return (m128) vec_add((uint64x2_t)a, (uint64x2_t)b);
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}
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static really_inline m128 and128(m128 a, m128 b) {
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return (m128) vandq_s8((int8x16_t)a, (int8x16_t)b);
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return (m128) vec_and((int8x16_t)a, (int8x16_t)b);
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}
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static really_inline m128 xor128(m128 a, m128 b) {
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return (m128) veorq_s8((int8x16_t)a, (int8x16_t)b);
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return (m128) vec_xor((int8x16_t)a, (int8x16_t)b);
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}
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static really_inline m128 or128(m128 a, m128 b) {
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return (m128) vorrq_s8((int8x16_t)a, (int8x16_t)b);
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return (m128) vec_or((int8x16_t)a, (int8x16_t)b);
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}
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static really_inline m128 andnot128(m128 a, m128 b) {
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return (m128) (m128) vandq_s8( vmvnq_s8(a), b);
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m128 and_res = and128(a,b);
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return (m128) not128(and_res);
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// or
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//return (m128) not128(and128(a,b));
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}
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// aligned load
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static really_inline m128 load128(const void *ptr) {
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assert(ISALIGNED_N(ptr, alignof(m128)));
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return (m128) vld1q_s32((const int32_t *)ptr);
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//return (m128) vld1q_s32((const int32_t *)ptr);
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//return *(int64x2_t *) (&ptr[0]);
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#warning FIXME
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}
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// aligned store
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static really_inline void store128(void *ptr, m128 a) {
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assert(ISALIGNED_N(ptr, alignof(m128)));
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vst1q_s32((int32_t *)ptr, a);
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//assert(ISALIGNED_N(ptr, alignof(m128)));
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//vst1q_s32((int32_t *)ptr, a);
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#warning FIXME
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}
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// unaligned load
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static really_inline m128 loadu128(const void *ptr) {
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return (m128) vld1q_s32((const int32_t *)ptr);
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//return (m128) vld1q_s32((const int32_t *)ptr);
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//return *(uint64x2_t *) (&ptr[0]);
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#warning FIXME
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}
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// unaligned store
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static really_inline void storeu128(void *ptr, m128 a) {
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vst1q_s32((int32_t *)ptr, a);
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//vst1q_s32((int32_t *)ptr, a);
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#warning FIXME
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}
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// packed unaligned store of first N bytes
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@@ -321,32 +361,41 @@ m128 palignr_imm(m128 r, m128 l, int offset) {
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static really_really_inline
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m128 palignr(m128 r, m128 l, int offset) {
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/*
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#if defined(HS_OPTIMIZE)
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return (m128)vextq_s8((int8x16_t)l, (int8x16_t)r, offset);
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#else
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return palignr_imm(r, l, offset);
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#endif
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*/
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#warning FIXME
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}
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#undef CASE_ALIGN_VECTORS
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static really_really_inline
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m128 rshiftbyte_m128(m128 a, unsigned b) {
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return palignr(zeroes128(), a, b);
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//return palignr(zeroes128(), a, b);
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#warning FIXME
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}
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static really_really_inline
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m128 lshiftbyte_m128(m128 a, unsigned b) {
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return palignr(a, zeroes128(), 16 - b);
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//return palignr(a, zeroes128(), 16 - b);
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#warning FIXME
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}
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static really_inline
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m128 variable_byte_shift_m128(m128 in, s32 amount) {
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/*
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assert(amount >= -16 && amount <= 16);
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static const uint8x16_t vbs_mask = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f };
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const uint8x16_t outside_mask = set1_16x8(0xf0);
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m128 shift_mask = palignr_imm(vbs_mask, outside_mask, 16 - amount);
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return vqtbl1q_s8(in, shift_mask);
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*/
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#warning FIXME
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}
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#ifdef __cplusplus
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@@ -381,7 +430,6 @@ void clearbit128(m128 *ptr, unsigned int n) {
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static really_inline
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char testbit128(m128 val, unsigned int n) {
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const m128 mask = mask1bit128(n);
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return isnonzero128(and128(mask, val));
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}
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@@ -390,40 +438,43 @@ m128 pshufb_m128(m128 a, m128 b) {
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/* On Intel, if bit 0x80 is set, then result is zero, otherwise which the lane it is &0xf.
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In NEON, if >=16, then the result is zero, otherwise it is that lane.
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btranslated is the version that is converted from Intel to NEON. */
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int8x16_t btranslated = vandq_s8((int8x16_t)b,vdupq_n_s8(0x8f));
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return (m128)vqtbl1q_s8((int8x16_t)a, (uint8x16_t)btranslated);
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//int8x16_t btranslated = vandq_s8((int8x16_t)b,vdupq_n_s8(0x8f));
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//return (m128)vqtbl1q_s8((int8x16_t)a, (uint8x16_t)btranslated);
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#warning FIXME
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}
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static really_inline
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m128 max_u8_m128(m128 a, m128 b) {
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return (m128) vmaxq_u8((int8x16_t)a, (int8x16_t)b);
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return (m128) vec_max((int8x16_t)a, (int8x16_t)b);
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}
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static really_inline
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m128 min_u8_m128(m128 a, m128 b) {
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return (m128) vminq_u8((int8x16_t)a, (int8x16_t)b);
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return (m128) vec_min((int8x16_t)a, (int8x16_t)b);
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}
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static really_inline
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m128 sadd_u8_m128(m128 a, m128 b) {
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return (m128) vqaddq_u8((uint8x16_t)a, (uint8x16_t)b);
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return (m128) vec_add((uint8x16_t)a, (uint8x16_t)b);
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}
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static really_inline
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m128 sub_u8_m128(m128 a, m128 b) {
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return (m128) vsubq_u8((uint8x16_t)a, (uint8x16_t)b);
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return (m128) vec_sub((uint8x16_t)a, (uint8x16_t)b);
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}
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static really_inline
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m128 set4x32(u32 x3, u32 x2, u32 x1, u32 x0) {
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uint32_t ALIGN_ATTR(16) data[4] = { x0, x1, x2, x3 };
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return (m128) vld1q_u32((uint32_t *) data);
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//uint32_t ALIGN_ATTR(16) data[4] = { x0, x1, x2, x3 };
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//return (m128) vld1q_u32((uint32_t *) data);
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#warning FIXME
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}
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static really_inline
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m128 set2x64(u64a hi, u64a lo) {
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uint64_t ALIGN_ATTR(16) data[2] = { lo, hi };
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return (m128) vld1q_u64((uint64_t *) data);
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//uint64_t ALIGN_ATTR(16) data[2] = { lo, hi };
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//return (m128) vld1q_u64((uint64_t *) data);
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#warning FIXME
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}
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#endif // ARCH_ARM_SIMD_UTILS_H
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#endif // ARCH_PPC64EL_SIMD_UTILS_H
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