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add arm support for the new SuperVector class
This commit is contained in:
Konstantinos Margaritis
parent
c6406bebde
commit
6e63aafbea
@ -36,6 +36,8 @@
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#if defined(__ARM_NEON) && (defined(ARCH_ARM32) || defined(ARCH_AARCH64))
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#define HAVE_NEON
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#define HAVE_SIMD_128_BITS
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#define CHUNKSIZE 128
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#define VECTORSIZE 16
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#endif
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#endif // UTIL_ARCH_ARM_H_
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259
src/util/simd/arch/arm/impl.hpp
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259
src/util/simd/arch/arm/impl.hpp
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@ -0,0 +1,259 @@
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/*
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* Copyright (c) 2015-2017, Intel Corporation
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* Copyright (c) 2020-2021, VectorCamp PC
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* * Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Intel Corporation nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef SIMD_IMPL_HPP
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#define SIMD_IMPL_HPP
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#include <cstdint>
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#include "util/simd/arch/arm/types.hpp"
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// 128-bit NEON implementation
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template<>
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really_inline SuperVector<16>::SuperVector(SuperVector const &o)
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{
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u.v128[0] = o.u.v128[0];
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}
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template<>
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really_inline SuperVector<16>::SuperVector(typename base_type::type const v)
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{
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u.v128[0] = v;
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};
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template<>
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template<>
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really_inline SuperVector<16>::SuperVector<int8x16_t>(int8x16_t const o)
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{
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u.v128[0] = static_cast<int32x4_t>(o);
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}
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template<>
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template<>
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really_inline SuperVector<16>::SuperVector<uint8x16_t>(uint8x16_t const o)
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{
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u.v128[0] = static_cast<int32x4_t>(o);
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}
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template<>
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template<>
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really_inline SuperVector<16>::SuperVector<int8_t>(int8_t const o)
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{
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u.v128[0] = vdupq_n_s8(o);
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}
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template<>
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template<>
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really_inline SuperVector<16>::SuperVector<uint8_t>(uint8_t const o)
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{
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u.v128[0] = vdupq_n_u8(o);
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}
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template<>
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template<>
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really_inline SuperVector<16>::SuperVector<int16_t>(int16_t const o)
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{
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u.v128[0] = vdupq_n_s16(o);
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}
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template<>
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template<>
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really_inline SuperVector<16>::SuperVector<uint16_t>(uint16_t const o)
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{
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u.v128[0] = vdupq_n_u16(o);
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}
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template<>
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template<>
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really_inline SuperVector<16>::SuperVector<int32_t>(int32_t const o)
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{
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u.v128[0] = vdupq_n_s32(o);
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}
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template<>
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template<>
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really_inline SuperVector<16>::SuperVector<uint32_t>(uint32_t const o)
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{
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u.v128[0] = vdupq_n_u32(o);
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}
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template<>
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template<>
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really_inline SuperVector<16>::SuperVector<int64_t>(int64_t const o)
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{
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u.v128[0] = vdupq_n_s64(o);
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}
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template<>
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template<>
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really_inline SuperVector<16>::SuperVector<uint64_t>(uint64_t const o)
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{
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u.v128[0] = vdupq_n_u64(o);
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}
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// Constants
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template<>
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really_inline SuperVector<16> SuperVector<16>::Ones(void)
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{
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return {vdupq_n_u8(0xFF)};
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}
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template<>
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really_inline SuperVector<16> SuperVector<16>::Zeroes(void)
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{
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return {vdupq_n_u8(0)};
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}
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template <>
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really_inline void SuperVector<16>::operator=(SuperVector<16> const &o)
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{
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u.v128[0] = o.u.v128[0];
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}
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template <>
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really_inline SuperVector<16> SuperVector<16>::operator&(SuperVector<16> const b) const
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{
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return {vandq_s8(u.v128[0], b.u.v128[0])};
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}
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template <>
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really_inline SuperVector<16> SuperVector<16>::eq(SuperVector<16> const b) const
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{
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return {vceqq_s8((int16x8_t)u.v128[0], (int16x8_t)b.u.v128[0])};
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}
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template <>
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really_inline typename SuperVector<16>::movemask_type SuperVector<16>::movemask(void) const
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{
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static const uint8x16_t powers{ 1, 2, 4, 8, 16, 32, 64, 128, 1, 2, 4, 8, 16, 32, 64, 128 };
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// Compute the mask from the input
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uint64x2_t mask = vpaddlq_u32(vpaddlq_u16(vpaddlq_u8(vandq_u8((uint16x8_t)u.v128[0], powers))));
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uint64x2_t mask1 = (m128)vextq_s8(mask, zeroes128(), 7);
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mask = vorrq_u8(mask, mask1);
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// Get the resulting bytes
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uint16_t output;
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vst1q_lane_u16((uint16_t*)&output, (uint16x8_t)mask, 0);
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return static_cast<typename SuperVector<16>::movemask_type>(output);
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}
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template <>
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really_inline typename SuperVector<16>::movemask_type SuperVector<16>::eqmask(SuperVector<16> const b) const
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{
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return eq(b).movemask();
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}
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#ifndef DEBUG
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template <>
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really_inline SuperVector<16> SuperVector<16>::operator<<(uint8_t const N) const
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{
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return {vshlq_n_s32(u.v128[0], N)};
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}
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#else
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template <>
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really_inline SuperVector<16> SuperVector<16>::operator<<(uint8_t const N) const
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{
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switch(N) {
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case 0: return *this; break;
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case 1: return {vshlq_n_s32((int16x8_t) u.v128[0], 1)}; break;
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case 2: return {vshlq_n_s32((int16x8_t) u.v128[0], 2)}; break;
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case 3: return {vshlq_n_s32((int16x8_t) u.v128[0], 3)}; break;
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case 4: return {vshlq_n_s32((int16x8_t) u.v128[0], 4)}; break;
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case 5: return {vshlq_n_s32((int16x8_t) u.v128[0], 5)}; break;
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case 6: return {vshlq_n_s32((int16x8_t) u.v128[0], 6)}; break;
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case 7: return {vshlq_n_s32((int16x8_t) u.v128[0], 7)}; break;
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case 8: return {vshlq_n_s32((int16x8_t) u.v128[0], 8)}; break;
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case 9: return {vshlq_n_s32((int16x8_t) u.v128[0], 9)}; break;
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case 10: return {vshlq_n_s32((int16x8_t) u.v128[0], 10)}; break;
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case 11: return {vshlq_n_s32((int16x8_t) u.v128[0], 11)}; break;
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case 12: return {vshlq_n_s32((int16x8_t) u.v128[0], 12)}; break;
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case 13: return {vshlq_n_s32((int16x8_t) u.v128[0], 13)}; break;
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case 14: return {vshlq_n_s32((int16x8_t) u.v128[0], 14)}; break;
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case 15: return {vshlq_n_s32((int16x8_t) u.v128[0], 15)}; break;
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case 16: return Zeroes(); break;
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default: break;
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}
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return *this;
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}
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#endif
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template <>
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really_inline SuperVector<16> SuperVector<16>::loadu(void const *ptr)
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{
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return {vld1q_s32((const int32_t *)ptr)};
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}
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template <>
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really_inline SuperVector<16> SuperVector<16>::load(void const *ptr)
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{
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assert(ISALIGNED_N(ptr, alignof(SuperVector::size)));
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ptr = assume_aligned(ptr, SuperVector::size);
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return vld1q_s32((const int32_t *)ptr);
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}
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#ifndef DEBUG
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template<>
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really_inline SuperVector<16> SuperVector<16>::alignr(SuperVector<16> r, int8_t offset)
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{
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return {vextq_s8((int16x8_t)u.v128[0], (int16x8_t)r.u.v128[0], offset)};
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}
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#else
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template<>
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really_inline SuperVector<16> SuperVector<16>::alignr(SuperVector<16> l, int8_t offset)
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{
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switch(offset) {
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case 0: return *this; break;
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case 1: return {vextq_s8((int16x8_t) u.v128[0], (int16x8_t) l.u.v128[0], 1)}; break;
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case 2: return {vextq_s8((int16x8_t) u.v128[0], (int16x8_t) l.u.v128[0], 2)}; break;
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case 3: return {vextq_s8((int16x8_t) u.v128[0], (int16x8_t) l.u.v128[0], 3)}; break;
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case 4: return {vextq_s8((int16x8_t) u.v128[0], (int16x8_t) l.u.v128[0], 4)}; break;
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case 5: return {vextq_s8((int16x8_t) u.v128[0], (int16x8_t) l.u.v128[0], 5)}; break;
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case 6: return {vextq_s8((int16x8_t) u.v128[0], (int16x8_t) l.u.v128[0], 6)}; break;
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case 7: return {vextq_s8((int16x8_t) u.v128[0], (int16x8_t) l.u.v128[0], 7)}; break;
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case 8: return {vextq_s8((int16x8_t) u.v128[0], (int16x8_t) l.u.v128[0], 8)}; break;
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case 9: return {vextq_s8((int16x8_t) u.v128[0], (int16x8_t) l.u.v128[0], 9)}; break;
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case 10: return {vextq_s8((int16x8_t) u.v128[0], (int16x8_t) l.u.v128[0], 10)}; break;
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case 11: return {vextq_s8((int16x8_t) u.v128[0], (int16x8_t) l.u.v128[0], 11)}; break;
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case 12: return {vextq_s8((int16x8_t) u.v128[0], (int16x8_t) l.u.v128[0], 12)}; break;
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case 13: return {vextq_s8((int16x8_t) u.v128[0], (int16x8_t) l.u.v128[0], 13)}; break;
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case 14: return {vextq_s8((int16x8_t) u.v128[0], (int16x8_t) l.u.v128[0], 14)}; break;
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case 15: return {vextq_s8((int16x8_t) u.v128[0], (int16x8_t) l.u.v128[0], 15)}; break;
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case 16: return l; break;
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default: break;
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}
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return *this;
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}
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#endif
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#endif // SIMD_IMPL_HPP
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33
src/util/simd/arch/arm/types.hpp
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33
src/util/simd/arch/arm/types.hpp
Normal file
@ -0,0 +1,33 @@
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/*
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* Copyright (c) 2015-2017, Intel Corporation
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* Copyright (c) 2020-2021, VectorCamp PC
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* * Redistributions of source code must retain the above copyright notice,
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||||
* this list of conditions and the following disclaimer.
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||||
* * Redistributions in binary form must reproduce the above copyright
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||||
* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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||||
* * Neither the name of Intel Corporation nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#if !defined(m128) && defined(HAVE_NEON)
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typedef int32x4_t m128;
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#endif
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