mirror of
https://github.com/VectorCamp/vectorscan.git
synced 2025-06-28 16:41:01 +03:00
Merge 77b17ae943d9f3118a07aebb8685120d795751b7 into c057c7f0f0f486656939359b863528fd58f838c3
This commit is contained in:
commit
53dc53e301
@ -31,7 +31,7 @@
|
||||
#include "ue2common.h"
|
||||
#include "util/arch.h"
|
||||
|
||||
#if !defined(HAVE_SSE42)
|
||||
#if (!defined(HAVE_SSE42)) || defined(VS_SIMDE_BACKEND)
|
||||
|
||||
/***
|
||||
*** What follows is derived from Intel's Slicing-by-8 CRC32 impl, which is BSD
|
||||
@ -586,7 +586,7 @@ u32 crc32c_sb8_64_bit(u32 running_crc, const unsigned char* p_buf,
|
||||
|
||||
// Externally visible function
|
||||
u32 Crc32c_ComputeBuf(u32 inCrc32, const void *buf, size_t bufLen) {
|
||||
#if defined(HAVE_SSE42)
|
||||
#if defined(HAVE_SSE42) && (!defined(VS_SIMDE_BACKEND))
|
||||
u32 crc = crc32c_sse42(inCrc32, (const unsigned char *)buf, bufLen);
|
||||
#else
|
||||
u32 crc = crc32c_sb8_64_bit(inCrc32, (const unsigned char *)buf, bufLen);
|
||||
|
@ -30,8 +30,12 @@
|
||||
#ifndef UTIL_ARCH_X86_CRC32_H_
|
||||
#define UTIL_ARCH_X86_CRC32_H_
|
||||
|
||||
#if defined(VS_SIMDE_BACKEND)
|
||||
#include "util/simd_types.h"
|
||||
#else
|
||||
#include "util/arch/x86/x86.h"
|
||||
#include "util/intrinsics.h"
|
||||
#endif
|
||||
|
||||
#ifdef ARCH_64_BIT
|
||||
#define CRC_WORD 8
|
||||
|
@ -39,7 +39,10 @@
|
||||
#ifndef VECTORSIZE
|
||||
#define VECTORSIZE 16
|
||||
#endif
|
||||
|
||||
#ifndef SIMDE_ENABLE_NATIVE_ALIASES
|
||||
#define SIMDE_ENABLE_NATIVE_ALIASES
|
||||
#endif
|
||||
#if !defined(VS_SIMDE_NATIVE)
|
||||
#define SIMDE_NO_NATIVE
|
||||
#endif
|
||||
|
Loading…
x
Reference in New Issue
Block a user