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DFA: use sherman economically

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Hong, Yang A 2020-06-18 09:48:52 +00:00
parent 475ad00f53
commit 15f0ccd1b8
2 changed files with 30 additions and 23 deletions
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6
src/nfa/mcclellancompile.cpp
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2015-2018, Intel Corporation * Copyright (c) 2015-2020, Intel Corporation
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
@ -1477,6 +1477,7 @@ bytecode_ptr<NFA> mcclellanCompile_i(raw_dfa &raw, accel_dfa_build_strat &strat,
bytecode_ptr<NFA> nfa; bytecode_ptr<NFA> nfa;
if (!using8bit) { if (!using8bit) {
// Wide state optimization
if (cc.grey.allowWideStates && strat.getType() == McClellan if (cc.grey.allowWideStates && strat.getType() == McClellan
&& !is_triggered(raw.kind)) { && !is_triggered(raw.kind)) {
find_wide_state(info); find_wide_state(info);
@ -1486,6 +1487,8 @@ bytecode_ptr<NFA> mcclellanCompile_i(raw_dfa &raw, accel_dfa_build_strat &strat,
bool any_cyclic_near_anchored_state bool any_cyclic_near_anchored_state
= is_cyclic_near(raw, raw.start_anchored); = is_cyclic_near(raw, raw.start_anchored);
// Sherman optimization
if (info.impl_alpha_size > 16) {
for (u32 i = 0; i < info.size(); i++) { for (u32 i = 0; i < info.size(); i++) {
if (info.is_widestate(i)) { if (info.is_widestate(i)) {
continue; continue;
@ -1499,6 +1502,7 @@ bytecode_ptr<NFA> mcclellanCompile_i(raw_dfa &raw, accel_dfa_build_strat &strat,
DEBUG_PRINTF("daddy %hu/%zu states=%zu alpha=%hu\n", total_daddy, DEBUG_PRINTF("daddy %hu/%zu states=%zu alpha=%hu\n", total_daddy,
info.size() * info.impl_alpha_size, info.size(), info.size() * info.impl_alpha_size, info.size(),
info.impl_alpha_size); info.impl_alpha_size);
}
nfa = mcclellanCompile16(info, cc, accel_states); nfa = mcclellanCompile16(info, cc, accel_states);
} else { } else {

5
src/nfa/mcsheng_compile.cpp
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2016-2017, Intel Corporation * Copyright (c) 2016-2020, Intel Corporation
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
@ -842,6 +842,8 @@ bytecode_ptr<NFA> mcshengCompile16(dfa_info &info, dstate_id_t sheng_end,
assert(info.getAlphaShift() <= 8); assert(info.getAlphaShift() <= 8);
// Sherman optimization
if (info.impl_alpha_size > 16) {
u16 total_daddy = 0; u16 total_daddy = 0;
for (u32 i = 0; i < info.size(); i++) { for (u32 i = 0; i < info.size(); i++) {
find_better_daddy(info, i, find_better_daddy(info, i,
@ -853,6 +855,7 @@ bytecode_ptr<NFA> mcshengCompile16(dfa_info &info, dstate_id_t sheng_end,
DEBUG_PRINTF("daddy %hu/%zu states=%zu alpha=%hu\n", total_daddy, DEBUG_PRINTF("daddy %hu/%zu states=%zu alpha=%hu\n", total_daddy,
info.size() * info.impl_alpha_size, info.size(), info.size() * info.impl_alpha_size, info.size(),
info.impl_alpha_size); info.impl_alpha_size);
}
u16 sherman_limit; u16 sherman_limit;
if (!allocateImplId16(info, sheng_end, &sherman_limit)) { if (!allocateImplId16(info, sheng_end, &sherman_limit)) {