mirror of
https://github.com/VectorCamp/vectorscan.git
synced 2025-09-30 03:34:25 +03:00
remove Windows/ICC support
This commit is contained in:
committed by
Konstantinos Margaritis
parent
8cff876962
commit
08357a096c
@@ -61,20 +61,12 @@ namespace ue2 {
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void *aligned_malloc_internal(size_t size, size_t align) {
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void *mem;
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#if !defined(_WIN32)
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int rv = posix_memalign(&mem, align, size);
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if (rv != 0) {
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DEBUG_PRINTF("posix_memalign returned %d when asked for %zu bytes\n",
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rv, size);
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return nullptr;
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}
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#else
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if (nullptr == (mem = _aligned_malloc(size, align))) {
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DEBUG_PRINTF("_aligned_malloc failed when asked for %zu bytes\n",
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size);
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return nullptr;
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}
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#endif
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assert(mem);
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return mem;
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@@ -85,11 +77,7 @@ void aligned_free_internal(void *ptr) {
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return;
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}
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#if defined(_WIN32)
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_aligned_free(ptr);
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#else
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free(ptr);
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#endif
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}
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/** \brief 64-byte aligned, zeroed malloc.
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@@ -31,7 +31,7 @@
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#include "ue2common.h"
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#if (defined(ARCH_IA32) || defined(ARCH_X86_64)) && !defined(_WIN32) && !defined(CPUID_H_)
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#if (defined(ARCH_IA32) || defined(ARCH_X86_64)) && !defined(CPUID_H_)
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#include <cpuid.h>
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/* system header doesn't have a header guard */
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#define CPUID_H_
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@@ -42,64 +42,23 @@
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static really_inline
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u32 clz32_impl(u32 x) {
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#if defined(_WIN32)
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unsigned long r;
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_BitScanReverse(&r, x);
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return 31 - r;
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#else
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return clz32_impl_c(x);
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#endif
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}
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static really_inline
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u32 clz64_impl(u64a x) {
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#if defined(_WIN64)
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unsigned long r;
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_BitScanReverse64(&r, x);
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return 63 - r;
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#elif defined(_WIN32)
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unsigned long x1 = (u32)x;
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unsigned long x2 = (u32)(x >> 32);
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unsigned long r;
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if (x2) {
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_BitScanReverse(&r, x2);
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return (u32)(31 - r);
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}
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_BitScanReverse(&r, (u32)x1);
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return (u32)(63 - r);
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#else
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return clz64_impl_c(x);
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#endif
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}
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// CTZ (count trailing zero) implementations.
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static really_inline
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u32 ctz32_impl(u32 x) {
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#if defined(_WIN32)
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unsigned long r;
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_BitScanForward(&r, x);
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return r;
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#else
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return ctz32_impl_c(x);
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#endif
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}
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static really_inline
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u32 ctz64_impl(u64a x) {
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#if defined(_WIN64)
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unsigned long r;
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_BitScanForward64(&r, x);
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return r;
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#elif defined(_WIN32)
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unsigned long r;
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if (_BitScanForward(&r, (u32)x)) {
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return (u32)r;
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}
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_BitScanForward(&r, x >> 32);
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return (u32)(r + 32);
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#else
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return ctz64_impl_c(x);
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#endif
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}
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static really_inline
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@@ -33,7 +33,7 @@
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#include "hs_internal.h"
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#include "util/arch.h"
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#if !defined(_WIN32) && !defined(CPUID_H_)
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#if !defined(CPUID_H_)
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#include <cpuid.h>
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#endif
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@@ -32,7 +32,7 @@
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#include "ue2common.h"
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#include "util/arch/common/cpuid_flags.h"
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#if !defined(_WIN32) && !defined(CPUID_H_)
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#if !defined(CPUID_H_)
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#include <cpuid.h>
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/* system header doesn't have a header guard */
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#define CPUID_H_
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@@ -46,16 +46,7 @@ extern "C"
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static inline
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void cpuid(unsigned int op, unsigned int leaf, unsigned int *eax,
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unsigned int *ebx, unsigned int *ecx, unsigned int *edx) {
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#ifndef _WIN32
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__cpuid_count(op, leaf, *eax, *ebx, *ecx, *edx);
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#else
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int a[4];
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__cpuidex(a, op, leaf);
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*eax = a[0];
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*ebx = a[1];
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*ecx = a[2];
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*edx = a[3];
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#endif
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}
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// ECX
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@@ -95,9 +86,6 @@ void cpuid(unsigned int op, unsigned int leaf, unsigned int *eax,
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static inline
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u64a xgetbv(u32 op) {
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#if defined(_WIN32) || defined(__INTEL_COMPILER)
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return _xgetbv(op);
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#else
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u32 a, d;
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__asm__ volatile (
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"xgetbv\n"
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@@ -105,14 +93,10 @@ u64a xgetbv(u32 op) {
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"=d"(d)
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: "c"(op));
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return ((u64a)d << 32) + a;
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#endif
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}
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static inline
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int check_avx2(void) {
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#if defined(__INTEL_COMPILER)
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return _may_i_use_cpu_feature(_FEATURE_AVX2);
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#else
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unsigned int eax, ebx, ecx, edx;
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cpuid(1, 0, &eax, &ebx, &ecx, &edx);
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@@ -141,7 +125,6 @@ int check_avx2(void) {
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}
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return 0;
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#endif
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}
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static inline
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@@ -149,9 +132,6 @@ int check_avx512(void) {
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/*
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* For our purposes, having avx512 really means "can we use AVX512BW?"
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*/
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#if defined(__INTEL_COMPILER)
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return _may_i_use_cpu_feature(_FEATURE_AVX512BW | _FEATURE_AVX512VL);
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#else
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unsigned int eax, ebx, ecx, edx;
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cpuid(1, 0, &eax, &ebx, &ecx, &edx);
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@@ -184,14 +164,10 @@ int check_avx512(void) {
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}
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return 0;
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#endif
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}
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static inline
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int check_avx512vbmi(void) {
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#if defined(__INTEL_COMPILER)
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return _may_i_use_cpu_feature(_FEATURE_AVX512VBMI);
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#else
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unsigned int eax, ebx, ecx, edx;
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cpuid(1, 0, &eax, &ebx, &ecx, &edx);
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@@ -229,7 +205,6 @@ int check_avx512vbmi(void) {
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}
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return 0;
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#endif
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}
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static inline
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@@ -38,12 +38,12 @@
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#define HAVE_SIMD_128_BITS
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#endif
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#if defined(__SSE4_1__) || (defined(_WIN32) && defined(__AVX__))
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#if defined(__SSE4_1__) || defined(__AVX__)
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#define HAVE_SSE41
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#define HAVE_SIMD_128_BITS
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#endif
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#if defined(__SSE4_2__) || (defined(_WIN32) && defined(__AVX__))
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#if defined(__SSE4_2__) || defined(__AVX__)
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#define HAVE_SSE42
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#define HAVE_SIMD_128_BITS
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#endif
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@@ -78,30 +78,16 @@
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#define VECTORSIZE 16
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#endif
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/*
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* ICC and MSVC don't break out POPCNT or BMI/2 as separate pre-def macros
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*/
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#if defined(__POPCNT__) || \
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(defined(__INTEL_COMPILER) && defined(__SSE4_2__)) || \
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(defined(_WIN32) && defined(__AVX__))
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#if defined(__POPCNT__)
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#define HAVE_POPCOUNT_INSTR
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#endif
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#if defined(__BMI__) || (defined(_WIN32) && defined(__AVX2__)) || \
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(defined(__INTEL_COMPILER) && defined(__AVX2__))
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#if defined(__BMI__)
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#define HAVE_BMI
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#endif
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#if defined(__BMI2__) || (defined(_WIN32) && defined(__AVX2__)) || \
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(defined(__INTEL_COMPILER) && defined(__AVX2__))
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#if defined(__BMI2__)
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#define HAVE_BMI2
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#endif
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/*
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* MSVC uses a different form of inline asm
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*/
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#if defined(_WIN32) && defined(_MSC_VER)
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#define NO_ASM
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#endif
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#endif // UTIL_ARCH_X86_H_
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@@ -56,11 +56,7 @@ void describeChar(ostream &os, char c, enum cc_output_t out_type) {
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const string backslash((out_type == CC_OUT_DOT ? 2 : 1), '\\');
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#ifdef _WIN32
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if (c >= 0x21 && c < 0x7F && c != '\\') {
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#else
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if (isgraph(c) && c != '\\') {
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#endif
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if (escaped.find(c) != string::npos) {
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os << backslash << c;
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} else if (out_type == CC_OUT_DOT
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@@ -1197,11 +1197,7 @@ u32 mmbit_sparse_iter_begin(const u8 *bits, u32 total_bits, u32 *idx,
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assert(ISALIGNED_N(it_root, alignof(struct mmbit_sparse_iter)));
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// Our state _may_ be on the stack
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#ifndef _WIN32
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assert(ISALIGNED_N(s, alignof(struct mmbit_sparse_state)));
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#else
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assert(ISALIGNED_N(s, 4));
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#endif
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MDEBUG_PRINTF("%p total_bits %u\n", bits, total_bits);
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// iterator should have _something_ at the root level
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@@ -1309,11 +1305,7 @@ u32 mmbit_sparse_iter_next(const u8 *bits, u32 total_bits, u32 last_key,
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assert(ISALIGNED_N(it_root, alignof(struct mmbit_sparse_iter)));
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// Our state _may_ be on the stack
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#ifndef _WIN32
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assert(ISALIGNED_N(s, alignof(struct mmbit_sparse_state)));
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#else
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assert(ISALIGNED_N(s, 4));
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#endif
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MDEBUG_PRINTF("%p total_bits %u\n", bits, total_bits);
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MDEBUG_PRINTF("NEXT (total_bits=%u, last_key=%u)\n", total_bits, last_key);
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@@ -1466,11 +1458,7 @@ void mmbit_sparse_iter_unset(u8 *bits, u32 total_bits,
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assert(ISALIGNED_N(it, alignof(struct mmbit_sparse_iter)));
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// Our state _may_ be on the stack
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#ifndef _WIN32
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assert(ISALIGNED_N(s, alignof(struct mmbit_sparse_state)));
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#else
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assert(ISALIGNED_N(s, 4));
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#endif
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MDEBUG_PRINTF("%p total_bits %u\n", bits, total_bits);
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@@ -38,36 +38,38 @@
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static really_inline
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u32 popcount32(u32 x) {
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#if defined(HAVE_POPCOUNT_INSTR)
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// Single-instruction builtin.
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return _mm_popcnt_u32(x);
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#else
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// Fast branch-free version from bit-twiddling hacks as older Intel
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// processors do not have a POPCNT instruction.
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x -= (x >> 1) & 0x55555555;
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x = (x & 0x33333333) + ((x >> 2) & 0x33333333);
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return (((x + (x >> 4)) & 0xf0f0f0f) * 0x1010101) >> 24;
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#endif
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return __builtin_popcount(x);
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// #if defined(HAVE_POPCOUNT_INSTR)
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// // Single-instruction builtin.
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// return _mm_popcnt_u32(x);
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// #else
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// // Fast branch-free version from bit-twiddling hacks as older Intel
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// // processors do not have a POPCNT instruction.
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// x -= (x >> 1) & 0x55555555;
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// x = (x & 0x33333333) + ((x >> 2) & 0x33333333);
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// return (((x + (x >> 4)) & 0xf0f0f0f) * 0x1010101) >> 24;
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// #endif
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}
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static really_inline
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u32 popcount64(u64a x) {
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#if defined(ARCH_X86_64)
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# if defined(HAVE_POPCOUNT_INSTR)
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// Single-instruction builtin.
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return (u32)_mm_popcnt_u64(x);
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# else
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// Fast branch-free version from bit-twiddling hacks as older Intel
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// processors do not have a POPCNT instruction.
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x -= (x >> 1) & 0x5555555555555555;
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x = (x & 0x3333333333333333) + ((x >> 2) & 0x3333333333333333);
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x = (x + (x >> 4)) & 0x0f0f0f0f0f0f0f0f;
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return (x * 0x0101010101010101) >> 56;
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# endif
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#else
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// Synthesise from two 32-bit cases.
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return popcount32(x >> 32) + popcount32(x);
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#endif
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return __builtin_popcountll(x);
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// #if defined(ARCH_X86_64)
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// # if defined(HAVE_POPCOUNT_INSTR)
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// // Single-instruction builtin.
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// return (u32)_mm_popcnt_u64(x);
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// # else
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// // Fast branch-free version from bit-twiddling hacks as older Intel
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// // processors do not have a POPCNT instruction.
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// x -= (x >> 1) & 0x5555555555555555;
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// x = (x & 0x3333333333333333) + ((x >> 2) & 0x3333333333333333);
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// x = (x + (x >> 4)) & 0x0f0f0f0f0f0f0f0f;
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// return (x * 0x0101010101010101) >> 56;
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// # endif
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// #else
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// // Synthesise from two 32-bit cases.
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// return popcount32(x >> 32) + popcount32(x);
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// #endif
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}
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#endif /* UTIL_POPCOUNT_H_ */
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@@ -35,12 +35,7 @@
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#include "ue2common.h"
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#if !defined(_WIN32)
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#define PACKED__MAY_ALIAS __attribute__((packed, may_alias))
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#else
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#define PACKED__MAY_ALIAS
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#pragma pack(push, 1) // pack everything until told otherwise
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#endif
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/// Perform an unaligned 16-bit load
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static really_inline
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@@ -89,9 +84,6 @@ void unaligned_store_u64a(void *ptr, u64a val) {
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struct unaligned *uptr = (struct unaligned *)ptr;
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uptr->u = val;
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}
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#if defined(_WIN32)
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#pragma pack(pop)
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#endif // win32
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#undef PACKED__MAY_ALIAS
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